oneblock1.v

用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过

module oneblock1(din,dout,keyin,keyout,roll,sel);  //one layer DES module 
input [0:63] din;
input [0:55] keyin;
input [2:0] roll;
input sel;        //encode or decode set bit
output [0:63] dout;
output [0:55] keyout;

wire [0:31] leftd,rightd,sd,pd;
wire [0:27] leftk,rightk;
reg [0:27] leftk2,rightk2;
wire [0:47] ed2,ed,ek;
wire [0:55] ktemp;

// call eight inst of S BOX
sbox11 box1(ed2[0:5],sd[0:3]);
sbox22 box2(ed2[6:11],sd[4:7]);
sbox33 box3(ed2[12:17],sd[8:11]);
sbox44 box4(ed2[18:23],sd[12:15]);
sbox55 box5(ed2[24:29],sd[16:19]);
sbox66 box6(ed2[30:35],sd[20:23]);
sbox77 box7(ed2[36:41],sd[24:27]);
sbox88 box8(ed2[42:47],sd[28:31]);

assign leftd=din[0:31];
assign rightd=din[32:63];
assign ed={rightd[31],rightd[0],rightd[1],rightd[2],rightd[3],rightd[4],rightd[3],rightd[4],
           rightd[5],rightd[6],rightd[7],rightd[8],rightd[7],rightd[8],rightd[9],rightd[10],
           rightd[11],rightd[12],rightd[11],rightd[12],rightd[13],rightd[14],rightd[15],rightd[16],
           rightd[15],rightd[16],rightd[17],rightd[18],rightd[19],rightd[20],rightd[19],rightd[20],
           rightd[21],rightd[22],rightd[23],rightd[24],rightd[23],rightd[24],rightd[25],rightd[26],
           rightd[27],rightd[28],rightd[27],rightd[28],rightd[29],rightd[30],rightd[31],rightd[0]};   //expand permutation

assign leftk=keyin[0:27];
assign rightk=keyin[28:55];

//according mode and shvar(roll) to set the key's shift bits
always @(sel or roll or leftk or rightk)
begin
  case({sel,roll[1:0]})
  3'b001:      //left shift 1
      begin
      leftk2={leftk[1:27],leftk[0]};
      rightk2={rightk[1:27],rightk[0]};
      end
  3'b010:      //left shift 2
      begin
      leftk2={leftk[2:27],leftk[0:1]};
      rightk2={rightk[2:27],leftk[0:1]};
      end
  3'b100:
      begin
      leftk2=leftk;
      rightk2=rightk;
      end
  3'b101:     //right shift 1
      begin
      leftk2={leftk[27],leftk[0:26]};
      rightk2={rightk[27],rightk[0:26]};
      end
  3'b110:    //right shift 2
      begin
      leftk2={leftk[26:27],leftk[0:25]};
      rightk2={rightk[26:27],rightk[0:25]};
      end
  default:
      begin
      leftk2=28'h0;
      rightk2=28'h0;
      end
  endcase
end

assign ktemp={leftk2,rightk2};
assign keyout=ktemp;

assign ek={ktemp[13],ktemp[16],ktemp[10],ktemp[23],ktemp[0],ktemp[4],ktemp[2],ktemp[27],
           ktemp[14],ktemp[5],ktemp[20],ktemp[9],ktemp[22],ktemp[18],ktemp[11],ktemp[3],
           ktemp[25],ktemp[7],ktemp[15],ktemp[6],ktemp[26],ktemp[19],ktemp[12],ktemp[1],
           ktemp[40],ktemp[51],ktemp[30],ktemp[36],ktemp[46],ktemp[54],ktemp[29],ktemp[39],
           ktemp[50],ktemp[44],ktemp[32],ktemp[47],ktemp[43],ktemp[48],ktemp[38],ktemp[55],
           ktemp[33],ktemp[52],ktemp[45],ktemp[41],ktemp[49],ktemp[35],ktemp[28],ktemp[31]}; //key compress&permutation
assign ed2=ed^ek;
assign pd={sd[15],sd[6],sd[19],sd[20],sd[28],sd[11],sd[27],sd[16],
           sd[0],sd[14],sd[22],sd[25],sd[4],sd[17],sd[30],sd[9],
           sd[1],sd[7],sd[23],sd[13],sd[31],sd[26],sd[2],sd[8],
           sd[18],sd[12],sd[29],sd[5],sd[21],sd[10],sd[3],sd[24]};  // P box permutation
assign dout=(roll[2])? {leftd^pd,rightd}:{rightd,leftd^pd};
endmodule