des.tan.qmsg

用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过

{ "Info" "ITDB_FULL_TCO_RESULT" "clk del kreg\[7\] 12.635 ns register " "Info: tco from clock \"clk\" to destination pin \"del\" through register \"kreg\[7\]\" is 12.635 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.978 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "" { clk } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 141 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 141; COMB Node = 'clk~clkctrl'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.666 ns) 2.978 ns kreg\[7\] 3 REG LCFF_X24_Y16_N25 5 " "Info: 3: + IC(1.073 ns) + CELL(0.666 ns) = 2.978 ns; Loc. = LCFF_X24_Y16_N25; Fanout = 5; REG Node = 'kreg\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "1.739 ns" { clk~clkctrl kreg[7] } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 59.30 % ) " "Info: Total cell delay = 1.766 ns ( 59.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.212 ns ( 40.70 % ) " "Info: Total interconnect delay = 1.212 ns ( 40.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "2.978 ns" { clk clk~clkctrl kreg[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "2.978 ns" { clk clk~combout clk~clkctrl kreg[7] } { 0.000ns 0.000ns 0.139ns 1.073ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.353 ns + Longest register pin " "Info: + Longest register to pin delay is 9.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kreg\[7\] 1 REG LCFF_X24_Y16_N25 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y16_N25; Fanout = 5; REG Node = 'kreg\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "" { kreg[7] } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.573 ns) + CELL(0.370 ns) 1.943 ns del~47 2 COMB LCCOMB_X24_Y17_N2 1 " "Info: 2: + IC(1.573 ns) + CELL(0.370 ns) = 1.943 ns; Loc. = LCCOMB_X24_Y17_N2; Fanout = 1; COMB Node = 'del~47'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "1.943 ns" { kreg[7] del~47 } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.206 ns) 3.236 ns del~6 3 COMB LCCOMB_X25_Y19_N4 1 " "Info: 3: + IC(1.087 ns) + CELL(0.206 ns) = 3.236 ns; Loc. = LCCOMB_X25_Y19_N4; Fanout = 1; COMB Node = 'del~6'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "1.293 ns" { del~47 del~6 } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.921 ns) + CELL(3.196 ns) 9.353 ns del 4 PIN PIN_H8 0 " "Info: 4: + IC(2.921 ns) + CELL(3.196 ns) = 9.353 ns; Loc. = PIN_H8; Fanout = 0; PIN Node = 'del'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "6.117 ns" { del~6 del } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.772 ns ( 40.33 % ) " "Info: Total cell delay = 3.772 ns ( 40.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.581 ns ( 59.67 % ) " "Info: Total interconnect delay = 5.581 ns ( 59.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "9.353 ns" { kreg[7] del~47 del~6 del } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.353 ns" { kreg[7] del~47 del~6 del } { 0.000ns 1.573ns 1.087ns 2.921ns } { 0.000ns 0.370ns 0.206ns 3.196ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "2.978 ns" { clk clk~clkctrl kreg[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "2.978 ns" { clk clk~combout clk~clkctrl kreg[7] } { 0.000ns 0.000ns 0.139ns 1.073ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "9.353 ns" { kreg[7] del~47 del~6 del } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.353 ns" { kreg[7] del~47 del~6 del } { 0.000ns 1.573ns 1.087ns 2.921ns } { 0.000ns 0.370ns 0.206ns 3.196ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dreg\[36\] din\[36\] clk -0.121 ns register " "Info: th for register \"dreg\[36\]\" (data pin = \"din\[36\]\", clock pin = \"clk\") is -0.121 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.972 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "" { clk } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G3 141 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 141; COMB Node = 'clk~clkctrl'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.666 ns) 2.972 ns dreg\[36\] 3 REG LCFF_X27_Y16_N11 5 " "Info: 3: + IC(1.067 ns) + CELL(0.666 ns) = 2.972 ns; Loc. = LCFF_X27_Y16_N11; Fanout = 5; REG Node = 'dreg\[36\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "1.733 ns" { clk~clkctrl dreg[36] } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 59.42 % ) " "Info: Total cell delay = 1.766 ns ( 59.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.206 ns ( 40.58 % ) " "Info: Total interconnect delay = 1.206 ns ( 40.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "2.972 ns" { clk clk~clkctrl dreg[36] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "2.972 ns" { clk clk~combout clk~clkctrl dreg[36] } { 0.000ns 0.000ns 0.139ns 1.067ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 33 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.399 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.070 ns) 1.070 ns din\[36\] 1 PIN PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.070 ns) = 1.070 ns; Loc. = PIN_W12; Fanout = 1; PIN Node = 'din\[36\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "" { din[36] } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(0.616 ns) 3.291 ns dreg\[36\]~426 2 COMB LCCOMB_X27_Y16_N10 1 " "Info: 2: + IC(1.605 ns) + CELL(0.616 ns) = 3.291 ns; Loc. = LCCOMB_X27_Y16_N10; Fanout = 1; COMB Node = 'dreg\[36\]~426'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "2.221 ns" { din[36] dreg[36]~426 } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.399 ns dreg\[36\] 3 REG LCFF_X27_Y16_N11 5 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.399 ns; Loc. = LCFF_X27_Y16_N11; Fanout = 5; REG Node = 'dreg\[36\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "0.108 ns" { dreg[36]~426 dreg[36] } "NODE_NAME" } "" } } { "DES.v" "" { Text "F:/altera/quartus51/mydesign/DES.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.794 ns ( 52.78 % ) " "Info: Total cell delay = 1.794 ns ( 52.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.605 ns ( 47.22 % ) " "Info: Total interconnect delay = 1.605 ns ( 47.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "3.399 ns" { din[36] dreg[36]~426 dreg[36] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.399 ns" { din[36] din[36]~combout dreg[36]~426 dreg[36] } { 0.000ns 0.000ns 1.605ns 0.000ns } { 0.000ns 1.070ns 0.616ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "2.972 ns" { clk clk~clkctrl dreg[36] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "2.972 ns" { clk clk~combout clk~clkctrl dreg[36] } { 0.000ns 0.000ns 0.139ns 1.067ns } { 0.000ns 1.100ns 0.000ns 0.666ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DES" "UNKNOWN" "V1" "F:/altera/quartus51/mydesign/db/DES.quartus_db" { Floorplan "F:/altera/quartus51/mydesign/" "" "3.399 ns" { din[36] dreg[36]~426 dreg[36] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.399 ns" { din[36] din[36]~combout dreg[36]~426 dreg[36] } { 0.000ns 0.000ns 1.605ns 0.000ns } { 0.000ns 1.070ns 0.616ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 17 14:02:52 2007 " "Info: Processing ended: Tue Jul 17 14:02:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}