des.tan.summary

来自「用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 20.380 ns
From           : mode
To             : dreg[37]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.635 ns
From           : kreg[7]
To             : del
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.121 ns
From           : din[36]
To             : dreg[36]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 58.70 MHz ( period = 17.037 ns )
From           : shvar[1]
To             : dreg[37]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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