calculater.v

来自「一个基于quartus2的等精度频率计的设计」· Verilog 代码 · 共 54 行

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
// Created on Sat Jul 07 09:58:45 2007

//  Module Declaration
module Calculater
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	Data1, Data2, Select, OUT
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [23:0] Data1;
	input [23:0] Data2;
	input [2:0] Select;
	output [7:0] OUT;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg [7:0] temp;
	
always @(Select)
	case(Select)
		3'b000: temp = Data1[7:0];
		3'b001: temp = Data1[15:8];
		3'b010: temp = Data1[23:16];
		3'b011: temp = 8'b0;
		3'b100: temp = Data2[7:0];
		3'b101: temp = Data2[15:8];
		3'b110: temp = Data2[23:16];
		3'b111: temp = 8'b0;
	endcase
	
assign OUT = temp;
endmodule