freq2.map.qmsg

一个基于quartus2的等精度频率计的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 09 11:00:18 2007 " "Info: Processing started: Mon Jul 09 11:00:18 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off freq2 -c freq2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freq2 -c freq2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BZ_block.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file BZ_block.v" { { "Info" "ISGN_ENTITY_NAME" "1 BZ_block " "Info: Found entity 1: BZ_block" {  } { { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Calculater.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Calculater.v" { { "Info" "ISGN_ENTITY_NAME" "1 Calculater " "Info: Found entity 1: Calculater" {  } { { "Calculater.v" "" { Text "D:/zx/quartus_project/freq2/Calculater.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DC_block.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DC_block.v" { { "Info" "ISGN_ENTITY_NAME" "1 DC_block " "Info: Found entity 1: DC_block" {  } { { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "M8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file M8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 M8 " "Info: Found entity 1: M8" {  } { { "M8.tdf" "" { Text "D:/zx/quartus_project/freq2/M8.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freq2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file freq2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 freq2 " "Info: Found entity 1: freq2" {  } { { "freq2.bdf" "" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "freq2 " "Info: Elaborating entity \"freq2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Calculater Calculater:inst2 " "Info: Elaborating entity \"Calculater\" for hierarchy \"Calculater:inst2\"" {  } { { "freq2.bdf" "inst2" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 208 600 760 304 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data1 Calculater.v(42) " "Warning (10235): Verilog HDL Always Construct warning at Calculater.v(42): variable \"Data1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Calculater.v" "" { Text "D:/zx/quartus_project/freq2/Calculater.v" 42 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data1 Calculater.v(43) " "Warning (10235): Verilog HDL Always Construct warning at Calculater.v(43): variable \"Data1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Calculater.v" "" { Text "D:/zx/quartus_project/freq2/Calculater.v" 43 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data1 Calculater.v(44) " "Warning (10235): Verilog HDL Always Construct warning at Calculater.v(44): variable \"Data1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Calculater.v" "" { Text "D:/zx/quartus_project/freq2/Calculater.v" 44 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data2 Calculater.v(46) " "Warning (10235): Verilog HDL Always Construct warning at Calculater.v(46): variable \"Data2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Calculater.v" "" { Text "D:/zx/quartus_project/freq2/Calculater.v" 46 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data2 Calculater.v(47) " "Warning (10235): Verilog HDL Always Construct warning at Calculater.v(47): variable \"Data2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Calculater.v" "" { Text "D:/zx/quartus_project/freq2/Calculater.v" 47 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data2 Calculater.v(48) " "Warning (10235): Verilog HDL Always Construct warning at Calculater.v(48): variable \"Data2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "Calculater.v" "" { Text "D:/zx/quartus_project/freq2/Calculater.v" 48 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BZ_block BZ_block:inst3 " "Info: Elaborating entity \"BZ_block\" for hierarchy \"BZ_block:inst3\"" {  } { { "freq2.bdf" "inst3" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 104 320 496 200 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "M8 M8:inst " "Info: Elaborating entity \"M8\" for hierarchy \"M8:inst\"" {  } { { "freq2.bdf" "inst" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 104 160 272 200 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter M8:inst\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"M8:inst\|lpm_counter:lpm_counter_component\"" {  } { { "M8.tdf" "lpm_counter_component" { Text "D:/zx/quartus_project/freq2/M8.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "M8:inst\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"M8:inst\|lpm_counter:lpm_counter_component\"" {  } { { "M8.tdf" "" { Text "D:/zx/quartus_project/freq2/M8.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0sh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_0sh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0sh " "Info: Found entity 1: cntr_0sh" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_0sh M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated " "Info: Elaborating entity \"cntr_0sh\" for hierarchy \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DC_block DC_block:inst1 " "Info: Elaborating entity \"DC_block\" for hierarchy \"DC_block:inst1\"" {  } { { "freq2.bdf" "inst1" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 320 328 512 416 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "118 " "Info: Implemented 118 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "103 " "Info: Implemented 103 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 09 11:00:20 2007 " "Info: Processing ended: Mon Jul 09 11:00:20 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}