freq2.hif

一个基于quartus2的等精度频率计的设计

USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_DEC
USR
trigger_level_pipeline
1
PARAMETER_DEC
USR
ela_status_bits
4
PARAMETER_DEC
USR
mem_address_bits
7
PARAMETER_DEC
USR
sample_depth
128
PARAMETER_DEC
USR
inversion_mask_length
52
PARAMETER_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000
PARAMETER_BIN
USR
power_up_trigger
0
PARAMETER_DEC
USR
 constraint(acq_trigger_in)
11 downto 0
PARAMETER_STRING
USR
 constraint(status)
3 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|freq2.(50).cnf
db|freq2.(50).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus60|libraries|megafunctions|sld_ela_control.vhd
50f992f5a51ab387a478321569ab2eee
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
4
PARAMETER_DEC
USR
ip_minor_version
0
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
data_bits
12
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
sync_enabled
1
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
USR
inversion_mask_length
52
PARAMETER_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000
PARAMETER_BIN
USR
power_up_trigger
0
PARAMETER_DEC
USR
 constraint(data_in)
11 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_ena)
0 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|freq2.(51).cnf
db|freq2.(51).cnf
# case_insensitive
# source_file
..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_shiftreg.tdf
5c3a6ccfa9758137252ac34dcc2420
6
# user_parameter {
LPM_WIDTH
36
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q35
-1
3
q34
-1
3
q33
-1
3
q32
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
load
-1
1
data9
-1
1
data8
-1
1
data7
-1
1
data6
-1
1
data5
-1
1
data4
-1
1
data35
-1
1
data34
-1
1
data33
-1
1
data32
-1
1
data31
-1
1
data30
-1
1
data3
-1
1
data29
-1
1
data28
-1
1
data27
-1
1
data26
-1
1
data25
-1
1
data24
-1
1
data23
-1
1
data22
-1
1
data21
-1
1
data20
-1
1
data2
-1
1
data19
-1
1
data18
-1
1
data17
-1
1
data16
-1
1
data15
-1
1
data14
-1
1
data13
-1
1
data12
-1
1
data11
-1
1
data10
-1
1
data1
-1
1
data0
-1
1
}
# include_file {
..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|program files|altera|quartus60|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
..|..|..|program files|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
}
# end
# entity
sld_mbpmg
# storage
db|freq2.(52).cnf
db|freq2.(52).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus60|libraries|megafunctions|sld_mbpmg.vhd
733528b384242eb705937dc92ca6446
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
4
PARAMETER_DEC
USR
ip_minor_version
0
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
data_bits
12
PARAMETER_DEC
USR
pattern_bits
3
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
sync_enabled
1
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
USR
 constraint(data_in)
11 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
35 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_acquisition_buffer
# storage
db|freq2.(53).cnf
db|freq2.(53).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|program files|altera|quartus60|libraries|megafunctions|sld_acquisition_buffer.vhd
8b25fa089aefba258e4cd917213af53
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
4
PARAMETER_DEC
USR
ip_minor_version
0
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
data_bits
12
PARAMETER_DEC
USR
buffer_depth
128
PARAMETER_DEC
USR
mem_address_bits
7
PARAMETER_DEC
USR
ela_status_bits
4
PARAMETER_DEC
USR
 constraint(status)
3 downto 0
PARAMETER_STRING
USR
 constraint(buffer_write_address)
6 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
6 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
6 downto 0
PARAMETER_STRING
USR
}
# end
# entity
altsyncram
# storage
db|freq2.(54).cnf
db|freq2.(54).cnf
# case_insensitive
# source_file
..|..|..|program files|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
12
PARAMETER_DEC
USR
WIDTHAD_B
7
PARAMETER_DEC
USR
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hji2
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|program files|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|program files|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|program files|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|program files|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|program files|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|program files|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|program files|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|program files|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_hji2
# storage
db|freq2.(55).cnf
db|freq2.(55).cnf
# case_insensitive
# source_file
db|altsyncram_hji2.tdf
a4e59970a376e249b4204399e717266e
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
sld_offload_buffer_mgr
# storage
db|freq2.(56).cnf
db|freq2.(56).cnf
# logic_option