cntr_9he.tdf

一个基于quartus2的等精度频率计的设计

--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" lpm_modulus=13 lpm_width=4 aclr clock q CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 8 
SUBDESIGN cntr_9he
( 
	aclr	:	input;
	clock	:	input;
	q[3..0]	:	output;
) 
VARIABLE
	cmpr1_aeb_int	:	WIRE;
	cmpr1_aeb	:	WIRE;
	cmpr1_dataa[3..0]	:	WIRE;
	cmpr1_datab[3..0]	:	WIRE;
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "11AA",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "12A0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	cout_bit : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "F8F8",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "off"
		);
	aclr_actual	: WIRE;
	clk_en	: NODE;
	compare_result	: WIRE;
	data[3..0]	: NODE;
	modulus_bus[3..0]	: WIRE;
	modulus_trigger	: WIRE;
	safe_q[3..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;
	time_to_clear	: WIRE;
	updownDir	: WIRE;

BEGIN 
	IF (cmpr1_dataa[] == cmpr1_datab[]) THEN
		cmpr1_aeb_int = VCC;
	ELSE
		cmpr1_aeb_int = GND;
	END IF;
	cmpr1_aeb = cmpr1_aeb_int;
	cmpr1_dataa[] = safe_q[];
	cmpr1_datab[] = modulus_bus[];
	counter_cella[3..0].aclr = aclr_actual;
	counter_cella[3..0].aload = B"0000";
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[3..0].clk = clock;
	counter_cella[3..0].dataa = safe_q[];
	counter_cella[3..0].datab = B"0000";
	counter_cella[3..0].datac = ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updownDir)));
	counter_cella[3..0].ena = clk_en;
	counter_cella[3..0].sclr = sclr;
	counter_cella[3..0].sload = (sload # modulus_trigger);
	cout_bit.cin = counter_cella[3].cout;
	cout_bit.dataa = updownDir;
	cout_bit.datab = time_to_clear;
	aclr_actual = aclr;
	clk_en = VCC;
	compare_result = cmpr1_aeb;
	data[] = GND;
	modulus_bus[] = B"1100";
	modulus_trigger = cout_bit.combout;
	q[] = safe_q[];
	safe_q[] = counter_cella[3..0].regout;
	sclr = GND;
	sload = GND;
	time_to_clear = compare_result;
	updownDir = B"1";
END;
--VALID FILE