freq2.tan.qmsg

一个基于quartus2的等精度频率计的设计

{ "Info" "ITDB_FULL_SLACK_RESULT" "fpgaclk register BZ_block:inst3\|temp\[3\] register BZ_block:inst3\|temp\[22\] 509 ps " "Info: Slack time is 509 ps for clock \"fpgaclk\" between source register \"BZ_block:inst3\|temp\[3\]\" and destination register \"BZ_block:inst3\|temp\[22\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.361 ns + Largest register register " "Info: + Largest register to register requirement is 3.361 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "4.000 ns + " "Info: + Setup relationship between source and destination is 4.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 4.000 ns " "Info: + Latch edge is 4.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination fpgaclk 4.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"fpgaclk\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source fpgaclk 4.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"fpgaclk\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.378 ns + Largest " "Info: + Largest clock skew is -0.378 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fpgaclk destination 8.610 ns + Shortest register " "Info: + Shortest clock path from clock \"fpgaclk\" to destination register is 8.610 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fpgaclk 1 CLK PIN_16 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 3; CLK Node = 'fpgaclk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fpgaclk } "NODE_NAME" } } { "freq2.bdf" "" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 128 -16 152 144 "fpgaclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[2\] 2 REG LC_X8_Y6_N8 3 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N8; Fanout = 3; REG Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 67 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.499 ns) + CELL(0.423 ns) 3.886 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUT 3 COMB LC_X8_Y6_N8 1 " "Info: 3: + IC(0.499 ns) + CELL(0.423 ns) = 3.886 ns; Loc. = LC_X8_Y6_N8; Fanout = 1; COMB Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUT'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.922 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.604 ns) 4.490 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|cout 4 COMB LC_X8_Y6_N9 24 " "Info: 4: + IC(0.000 ns) + CELL(0.604 ns) = 4.490 ns; Loc. = LC_X8_Y6_N9; Fanout = 24; COMB Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|cout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.604 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 91 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.409 ns) + CELL(0.711 ns) 8.610 ns BZ_block:inst3\|temp\[22\] 5 REG LC_X24_Y5_N5 4 " "Info: 5: + IC(3.409 ns) + CELL(0.711 ns) = 8.610 ns; Loc. = LC_X24_Y5_N5; Fanout = 4; REG Node = 'BZ_block:inst3\|temp\[22\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.120 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.142 ns ( 48.11 % ) " "Info: Total cell delay = 4.142 ns ( 48.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.468 ns ( 51.89 % ) " "Info: Total interconnect delay = 4.468 ns ( 51.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.610 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.610 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } { 0.000ns 0.000ns 0.560ns 0.499ns 0.000ns 3.409ns } { 0.000ns 1.469ns 0.935ns 0.423ns 0.604ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fpgaclk source 8.988 ns - Longest register " "Info: - Longest clock path from clock \"fpgaclk\" to source register is 8.988 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fpgaclk 1 CLK PIN_16 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 3; CLK Node = 'fpgaclk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fpgaclk } "NODE_NAME" } } { "freq2.bdf" "" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 128 -16 152 144 "fpgaclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[0\] 2 REG LC_X8_Y6_N6 3 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N6; Fanout = 3; REG Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 67 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 4.062 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella0~COUTCOUT1_5 3 COMB LC_X8_Y6_N6 2 " "Info: 3: + IC(0.523 ns) + CELL(0.575 ns) = 4.062 ns; Loc. = LC_X8_Y6_N6; Fanout = 2; COMB Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella0~COUTCOUT1_5'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.098 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.142 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUTCOUT1_3 4 COMB LC_X8_Y6_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 4.142 ns; Loc. = LC_X8_Y6_N7; Fanout = 2; COMB Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUTCOUT1_3'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.222 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUTCOUT1_5 5 COMB LC_X8_Y6_N8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 4.222 ns; Loc. = LC_X8_Y6_N8; Fanout = 1; COMB Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUTCOUT1_5'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 4.830 ns M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|cout 6 COMB LC_X8_Y6_N9 24 " "Info: 6: + IC(0.000 ns) + CELL(0.608 ns) = 4.830 ns; Loc. = LC_X8_Y6_N9; Fanout = 24; COMB Node = 'M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|cout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.608 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout } "NODE_NAME" } } { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 91 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.447 ns) + CELL(0.711 ns) 8.988 ns BZ_block:inst3\|temp\[3\] 7 REG LC_X24_Y7_N6 4 " "Info: 7: + IC(3.447 ns) + CELL(0.711 ns) = 8.988 ns; Loc. = LC_X24_Y7_N6; Fanout = 4; REG Node = 'BZ_block:inst3\|temp\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.158 ns" { M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.458 ns ( 49.60 % ) " "Info: Total cell delay = 4.458 ns ( 49.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.530 ns ( 50.40 % ) " "Info: Total interconnect delay = 4.530 ns ( 50.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.988 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.988 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } { 0.000ns 0.000ns 0.560ns 0.523ns 0.000ns 0.000ns 0.000ns 3.447ns } { 0.000ns 1.469ns 0.935ns 0.575ns 0.080ns 0.080ns 0.608ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.610 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.610 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } { 0.000ns 0.000ns 0.560ns 0.499ns 0.000ns 3.409ns } { 0.000ns 1.469ns 0.935ns 0.423ns 0.604ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.988 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.988 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } { 0.000ns 0.000ns 0.560ns 0.523ns 0.000ns 0.000ns 0.000ns 3.447ns } { 0.000ns 1.469ns 0.935ns 0.575ns 0.080ns 0.080ns 0.608ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.610 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.610 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } { 0.000ns 0.000ns 0.560ns 0.499ns 0.000ns 3.409ns } { 0.000ns 1.469ns 0.935ns 0.423ns 0.604ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.988 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.988 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } { 0.000ns 0.000ns 0.560ns 0.523ns 0.000ns 0.000ns 0.000ns 3.447ns } { 0.000ns 1.469ns 0.935ns 0.575ns 0.080ns 0.080ns 0.608ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.852 ns - Longest register register " "Info: - Longest register to register delay is 2.852 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BZ_block:inst3\|temp\[3\] 1 REG LC_X24_Y7_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y7_N6; Fanout = 4; REG Node = 'BZ_block:inst3\|temp\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BZ_block:inst3|temp[3] } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.575 ns) 1.115 ns BZ_block:inst3\|temp\[3\]~1444COUT1_1509 2 COMB LC_X24_Y7_N6 2 " "Info: 2: + IC(0.540 ns) + CELL(0.575 ns) = 1.115 ns; Loc. = LC_X24_Y7_N6; Fanout = 2; COMB Node = 'BZ_block:inst3\|temp\[3\]~1444COUT1_1509'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.115 ns" { BZ_block:inst3|temp[3] BZ_block:inst3|temp[3]~1444COUT1_1509 } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.195 ns BZ_block:inst3\|temp\[4\]~1441COUT1_1511 3 COMB LC_X24_Y7_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.195 ns; Loc. = LC_X24_Y7_N7; Fanout = 2; COMB Node = 'BZ_block:inst3\|temp\[4\]~1441COUT1_1511'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { BZ_block:inst3|temp[3]~1444COUT1_1509 BZ_block:inst3|temp[4]~1441COUT1_1511 } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.275 ns BZ_block:inst3\|temp\[5\]~1438COUT1_1513 4 COMB LC_X24_Y7_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.275 ns; Loc. = LC_X24_Y7_N8; Fanout = 2; COMB Node = 'BZ_block:inst3\|temp\[5\]~1438COUT1_1513'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { BZ_block:inst3|temp[4]~1441COUT1_1511 BZ_block:inst3|temp[5]~1438COUT1_1513 } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.533 ns BZ_block:inst3\|temp\[6\]~1435 5 COMB LC_X24_Y7_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.533 ns; Loc. = LC_X24_Y7_N9; Fanout = 6; COMB Node = 'BZ_block:inst3\|temp\[6\]~1435'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { BZ_block:inst3|temp[5]~1438COUT1_1513 BZ_block:inst3|temp[6]~1435 } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.669 ns BZ_block:inst3\|temp\[11\]~1442 6 COMB LC_X24_Y6_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.669 ns; Loc. = LC_X24_Y6_N4; Fanout = 6; COMB Node = 'BZ_block:inst3\|temp\[11\]~1442'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { BZ_block:inst3|temp[6]~1435 BZ_block:inst3|temp[11]~1442 } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.877 ns BZ_block:inst3\|temp\[16\]~1452 7 COMB LC_X24_Y6_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 1.877 ns; Loc. = LC_X24_Y6_N9; Fanout = 6; COMB Node = 'BZ_block:inst3\|temp\[16\]~1452'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { BZ_block:inst3|temp[11]~1442 BZ_block:inst3|temp[16]~1452 } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.013 ns BZ_block:inst3\|temp\[21\]~1437 8 COMB LC_X24_Y5_N4 2 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 2.013 ns; Loc. = LC_X24_Y5_N4; Fanout = 2; COMB Node = 'BZ_block:inst3\|temp\[21\]~1437'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { BZ_block:inst3|temp[16]~1452 BZ_block:inst3|temp[21]~1437 } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.852 ns BZ_block:inst3\|temp\[22\] 9 REG LC_X24_Y5_N5 4 " "Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 2.852 ns; Loc. = LC_X24_Y5_N5; Fanout = 4; REG Node = 'BZ_block:inst3\|temp\[22\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { BZ_block:inst3|temp[21]~1437 BZ_block:inst3|temp[22] } "NODE_NAME" } } { "BZ_block.v" "" { Text "D:/zx/quartus_project/freq2/BZ_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.312 ns ( 81.07 % ) " "Info: Total cell delay = 2.312 ns ( 81.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.540 ns ( 18.93 % ) " "Info: Total interconnect delay = 0.540 ns ( 18.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.852 ns" { BZ_block:inst3|temp[3] BZ_block:inst3|temp[3]~1444COUT1_1509 BZ_block:inst3|temp[4]~1441COUT1_1511 BZ_block:inst3|temp[5]~1438COUT1_1513 BZ_block:inst3|temp[6]~1435 BZ_block:inst3|temp[11]~1442 BZ_block:inst3|temp[16]~1452 BZ_block:inst3|temp[21]~1437 BZ_block:inst3|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.852 ns" { BZ_block:inst3|temp[3] BZ_block:inst3|temp[3]~1444COUT1_1509 BZ_block:inst3|temp[4]~1441COUT1_1511 BZ_block:inst3|temp[5]~1438COUT1_1513 BZ_block:inst3|temp[6]~1435 BZ_block:inst3|temp[11]~1442 BZ_block:inst3|temp[16]~1452 BZ_block:inst3|temp[21]~1437 BZ_block:inst3|temp[22] } { 0.000ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.610 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.610 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[2] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUT M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[22] } { 0.000ns 0.000ns 0.560ns 0.499ns 0.000ns 3.409ns } { 0.000ns 1.469ns 0.935ns 0.423ns 0.604ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.988 ns" { fpgaclk M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.988 ns" { fpgaclk fpgaclk~out0 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|safe_q[0] M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella0~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella1~COUTCOUT1_3 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|counter_cella2~COUTCOUT1_5 M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated|cout BZ_block:inst3|temp[3] } { 0.000ns 0.000ns 0.560ns 0.523ns 0.000ns 0.000ns 0.000ns 3.447ns } { 0.000ns 1.469ns 0.935ns 0.575ns 0.080ns 0.080ns 0.608ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.852 ns" { BZ_block:inst3|temp[3] BZ_block:inst3|temp[3]~1444COUT1_1509 BZ_block:inst3|temp[4]~1441COUT1_1511 BZ_block:inst3|temp[5]~1438COUT1_1513 BZ_block:inst3|temp[6]~1435 BZ_block:inst3|temp[11]~1442 BZ_block:inst3|temp[16]~1452 BZ_block:inst3|temp[21]~1437 BZ_block:inst3|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.852 ns" { BZ_block:inst3|temp[3] BZ_block:inst3|temp[3]~1444COUT1_1509 BZ_block:inst3|temp[4]~1441COUT1_1511 BZ_block:inst3|temp[5]~1438COUT1_1513 BZ_block:inst3|temp[6]~1435 BZ_block:inst3|temp[11]~1442 BZ_block:inst3|temp[16]~1452 BZ_block:inst3|temp[21]~1437 BZ_block:inst3|temp[22] } { 0.000ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register DC_block:inst1\|temp\[23\] register DC_block:inst1\|temp\[23\] 1.057 ns " "Info: Minimum slack time is 1.057 ns for clock \"clk\" between source register \"DC_block:inst1\|temp\[23\]\" and destination register \"DC_block:inst1\|temp\[23\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.848 ns + Shortest register register " "Info: + Shortest register to register delay is 0.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DC_block:inst1\|temp\[23\] 1 REG LC_X25_Y5_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y5_N6; Fanout = 2; REG Node = 'DC_block:inst1\|temp\[23\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DC_block:inst1|temp[23] } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.309 ns) 0.848 ns DC_block:inst1\|temp\[23\] 2 REG LC_X25_Y5_N6 2 " "Info: 2: + IC(0.539 ns) + CELL(0.309 ns) = 0.848 ns; Loc. = LC_X25_Y5_N6; Fanout = 2; REG Node = 'DC_block:inst1\|temp\[23\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.848 ns" { DC_block:inst1|temp[23] DC_block:inst1|temp[23] } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 36.44 % ) " "Info: Total cell delay = 0.309 ns ( 36.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.539 ns ( 63.56 % ) " "Info: Total interconnect delay = 0.539 ns ( 63.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.848 ns" { DC_block:inst1|temp[23] DC_block:inst1|temp[23] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "0.848 ns" { DC_block:inst1|temp[23] DC_block:inst1|temp[23] } { 0.000ns 0.539ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 4.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 4.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_38 25 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq2.bdf" "" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 248 -24 144 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.075 ns) + CELL(0.711 ns) 7.261 ns DC_block:inst1\|temp\[23\] 2 REG LC_X25_Y5_N6 2 " "Info: 2: + IC(5.075 ns) + CELL(0.711 ns) = 7.261 ns; Loc. = LC_X25_Y5_N6; Fanout = 2; REG Node = 'DC_block:inst1\|temp\[23\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.786 ns" { clk DC_block:inst1|temp[23] } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 30.11 % ) " "Info: Total cell delay = 2.186 ns ( 30.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.075 ns ( 69.89 % ) " "Info: Total interconnect delay = 5.075 ns ( 69.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.261 ns" { clk DC_block:inst1|temp[23] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.261 ns" { clk clk~out0 DC_block:inst1|temp[23] } { 0.000ns 0.000ns 5.075ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.261 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_38 25 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld