freq2.tan.qmsg

一个基于quartus2的等精度频率计的设计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[0\] " "Info: Detected ripple clock \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[0\]\" as buffer" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 67 8 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[1\] " "Info: Detected ripple clock \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[1\]\" as buffer" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 67 8 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUTCOUT1_3 " "Info: Detected gated clock \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUTCOUT1_3\" as buffer" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 39 2 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUTCOUT1_3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUT " "Info: Detected gated clock \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUT\" as buffer" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 39 2 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella1~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[2\] " "Info: Detected ripple clock \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[2\]\" as buffer" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 67 8 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|safe_q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUTCOUT1_5 " "Info: Detected gated clock \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUTCOUT1_5\" as buffer" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 47 2 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUTCOUT1_5" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUT " "Info: Detected gated clock \"M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUT\" as buffer" {  } { { "db/cntr_0sh.tdf" "" { Text "D:/zx/quartus_project/freq2/db/cntr_0sh.tdf" 47 2 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "M8:inst\|lpm_counter:lpm_counter_component\|cntr_0sh:auto_generated\|counter_cella2~COUT" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register DC_block:inst1\|temp\[3\] register DC_block:inst1\|temp\[22\] 860 ps " "Info: Slack time is 860 ps for clock \"clk\" between source register \"DC_block:inst1\|temp\[3\]\" and destination register \"DC_block:inst1\|temp\[22\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.701 ns + Largest register register " "Info: + Largest register to register requirement is 3.701 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "4.000 ns + " "Info: + Setup relationship between source and destination is 4.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 4.000 ns " "Info: + Latch edge is 4.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 4.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 4.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.038 ns + Largest " "Info: + Largest clock skew is -0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.261 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_38 25 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq2.bdf" "" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 248 -24 144 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.075 ns) + CELL(0.711 ns) 7.261 ns DC_block:inst1\|temp\[22\] 2 REG LC_X25_Y5_N5 4 " "Info: 2: + IC(5.075 ns) + CELL(0.711 ns) = 7.261 ns; Loc. = LC_X25_Y5_N5; Fanout = 4; REG Node = 'DC_block:inst1\|temp\[22\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.786 ns" { clk DC_block:inst1|temp[22] } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 30.11 % ) " "Info: Total cell delay = 2.186 ns ( 30.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.075 ns ( 69.89 % ) " "Info: Total interconnect delay = 5.075 ns ( 69.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.261 ns" { clk DC_block:inst1|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.261 ns" { clk clk~out0 DC_block:inst1|temp[22] } { 0.000ns 0.000ns 5.075ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.299 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.299 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_38 25 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq2.bdf" "" { Schematic "D:/zx/quartus_project/freq2/freq2.bdf" { { 248 -24 144 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.113 ns) + CELL(0.711 ns) 7.299 ns DC_block:inst1\|temp\[3\] 2 REG LC_X25_Y7_N6 4 " "Info: 2: + IC(5.113 ns) + CELL(0.711 ns) = 7.299 ns; Loc. = LC_X25_Y7_N6; Fanout = 4; REG Node = 'DC_block:inst1\|temp\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.824 ns" { clk DC_block:inst1|temp[3] } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.95 % ) " "Info: Total cell delay = 2.186 ns ( 29.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.113 ns ( 70.05 % ) " "Info: Total interconnect delay = 5.113 ns ( 70.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.299 ns" { clk DC_block:inst1|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.299 ns" { clk clk~out0 DC_block:inst1|temp[3] } { 0.000ns 0.000ns 5.113ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.261 ns" { clk DC_block:inst1|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.261 ns" { clk clk~out0 DC_block:inst1|temp[22] } { 0.000ns 0.000ns 5.075ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.299 ns" { clk DC_block:inst1|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.299 ns" { clk clk~out0 DC_block:inst1|temp[3] } { 0.000ns 0.000ns 5.113ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.261 ns" { clk DC_block:inst1|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.261 ns" { clk clk~out0 DC_block:inst1|temp[22] } { 0.000ns 0.000ns 5.075ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.299 ns" { clk DC_block:inst1|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.299 ns" { clk clk~out0 DC_block:inst1|temp[3] } { 0.000ns 0.000ns 5.113ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.841 ns - Longest register register " "Info: - Longest register to register delay is 2.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DC_block:inst1\|temp\[3\] 1 REG LC_X25_Y7_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y7_N6; Fanout = 4; REG Node = 'DC_block:inst1\|temp\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DC_block:inst1|temp[3] } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.575 ns) 1.104 ns DC_block:inst1\|temp\[3\]~132COUT1_197 2 COMB LC_X25_Y7_N6 2 " "Info: 2: + IC(0.529 ns) + CELL(0.575 ns) = 1.104 ns; Loc. = LC_X25_Y7_N6; Fanout = 2; COMB Node = 'DC_block:inst1\|temp\[3\]~132COUT1_197'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.104 ns" { DC_block:inst1|temp[3] DC_block:inst1|temp[3]~132COUT1_197 } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.184 ns DC_block:inst1\|temp\[4\]~129COUT1_199 3 COMB LC_X25_Y7_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.184 ns; Loc. = LC_X25_Y7_N7; Fanout = 2; COMB Node = 'DC_block:inst1\|temp\[4\]~129COUT1_199'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { DC_block:inst1|temp[3]~132COUT1_197 DC_block:inst1|temp[4]~129COUT1_199 } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.264 ns DC_block:inst1\|temp\[5\]~126COUT1_201 4 COMB LC_X25_Y7_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.264 ns; Loc. = LC_X25_Y7_N8; Fanout = 2; COMB Node = 'DC_block:inst1\|temp\[5\]~126COUT1_201'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { DC_block:inst1|temp[4]~129COUT1_199 DC_block:inst1|temp[5]~126COUT1_201 } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.522 ns DC_block:inst1\|temp\[6\]~123 5 COMB LC_X25_Y7_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.522 ns; Loc. = LC_X25_Y7_N9; Fanout = 6; COMB Node = 'DC_block:inst1\|temp\[6\]~123'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { DC_block:inst1|temp[5]~126COUT1_201 DC_block:inst1|temp[6]~123 } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.658 ns DC_block:inst1\|temp\[11\]~130 6 COMB LC_X25_Y6_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.658 ns; Loc. = LC_X25_Y6_N4; Fanout = 6; COMB Node = 'DC_block:inst1\|temp\[11\]~130'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { DC_block:inst1|temp[6]~123 DC_block:inst1|temp[11]~130 } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.866 ns DC_block:inst1\|temp\[16\]~140 7 COMB LC_X25_Y6_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 1.866 ns; Loc. = LC_X25_Y6_N9; Fanout = 6; COMB Node = 'DC_block:inst1\|temp\[16\]~140'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { DC_block:inst1|temp[11]~130 DC_block:inst1|temp[16]~140 } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.002 ns DC_block:inst1\|temp\[21\]~125 8 COMB LC_X25_Y5_N4 2 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 2.002 ns; Loc. = LC_X25_Y5_N4; Fanout = 2; COMB Node = 'DC_block:inst1\|temp\[21\]~125'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { DC_block:inst1|temp[16]~140 DC_block:inst1|temp[21]~125 } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.841 ns DC_block:inst1\|temp\[22\] 9 REG LC_X25_Y5_N5 4 " "Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 2.841 ns; Loc. = LC_X25_Y5_N5; Fanout = 4; REG Node = 'DC_block:inst1\|temp\[22\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { DC_block:inst1|temp[21]~125 DC_block:inst1|temp[22] } "NODE_NAME" } } { "DC_block.v" "" { Text "D:/zx/quartus_project/freq2/DC_block.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.312 ns ( 81.38 % ) " "Info: Total cell delay = 2.312 ns ( 81.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns ( 18.62 % ) " "Info: Total interconnect delay = 0.529 ns ( 18.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.841 ns" { DC_block:inst1|temp[3] DC_block:inst1|temp[3]~132COUT1_197 DC_block:inst1|temp[4]~129COUT1_199 DC_block:inst1|temp[5]~126COUT1_201 DC_block:inst1|temp[6]~123 DC_block:inst1|temp[11]~130 DC_block:inst1|temp[16]~140 DC_block:inst1|temp[21]~125 DC_block:inst1|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.841 ns" { DC_block:inst1|temp[3] DC_block:inst1|temp[3]~132COUT1_197 DC_block:inst1|temp[4]~129COUT1_199 DC_block:inst1|temp[5]~126COUT1_201 DC_block:inst1|temp[6]~123 DC_block:inst1|temp[11]~130 DC_block:inst1|temp[16]~140 DC_block:inst1|temp[21]~125 DC_block:inst1|temp[22] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.261 ns" { clk DC_block:inst1|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.261 ns" { clk clk~out0 DC_block:inst1|temp[22] } { 0.000ns 0.000ns 5.075ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.299 ns" { clk DC_block:inst1|temp[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.299 ns" { clk clk~out0 DC_block:inst1|temp[3] } { 0.000ns 0.000ns 5.113ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.841 ns" { DC_block:inst1|temp[3] DC_block:inst1|temp[3]~132COUT1_197 DC_block:inst1|temp[4]~129COUT1_199 DC_block:inst1|temp[5]~126COUT1_201 DC_block:inst1|temp[6]~123 DC_block:inst1|temp[11]~130 DC_block:inst1|temp[16]~140 DC_block:inst1|temp[21]~125 DC_block:inst1|temp[22] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.841 ns" { DC_block:inst1|temp[3] DC_block:inst1|temp[3]~132COUT1_197 DC_block:inst1|temp[4]~129COUT1_199 DC_block:inst1|temp[5]~126COUT1_201 DC_block:inst1|temp[6]~123 DC_block:inst1|temp[11]~130 DC_block:inst1|temp[16]~140 DC_block:inst1|temp[21]~125 DC_block:inst1|temp[22] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}