freq2.tan.rpt

一个基于quartus2的等精度频率计的设计

+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 250 MHz            ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; 250.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; fpgaclk         ;                    ; User Pin ; 250.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                    ; To                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 0.860 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[22] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.841 ns                ;
; 0.860 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[23] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.841 ns                ;
; 0.908 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[0]  ; DC_block:inst1|temp[22] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.793 ns                ;
; 0.908 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[0]  ; DC_block:inst1|temp[23] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.793 ns                ;
; 0.931 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[4]  ; DC_block:inst1|temp[22] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.770 ns                ;
; 0.931 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[4]  ; DC_block:inst1|temp[23] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.770 ns                ;
; 0.937 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[17] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.764 ns                ;
; 0.937 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[18] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.764 ns                ;
; 0.937 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[19] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.764 ns                ;
; 0.937 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[20] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.764 ns                ;
; 0.937 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[21] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.764 ns                ;
; 0.942 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[2]  ; DC_block:inst1|temp[22] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.759 ns                ;
; 0.942 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[2]  ; DC_block:inst1|temp[23] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.759 ns                ;
; 0.985 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[0]  ; DC_block:inst1|temp[17] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.716 ns                ;
; 0.985 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[0]  ; DC_block:inst1|temp[18] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.716 ns                ;
; 0.985 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[0]  ; DC_block:inst1|temp[19] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.716 ns                ;
; 0.985 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[0]  ; DC_block:inst1|temp[20] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.716 ns                ;
; 0.985 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[0]  ; DC_block:inst1|temp[21] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.716 ns                ;
; 1.004 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[6]  ; DC_block:inst1|temp[22] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.697 ns                ;
; 1.004 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[6]  ; DC_block:inst1|temp[23] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.697 ns                ;
; 1.008 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[4]  ; DC_block:inst1|temp[17] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.693 ns                ;
; 1.008 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[4]  ; DC_block:inst1|temp[18] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.693 ns                ;
; 1.008 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[4]  ; DC_block:inst1|temp[19] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.693 ns                ;
; 1.008 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[4]  ; DC_block:inst1|temp[20] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.693 ns                ;
; 1.008 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[4]  ; DC_block:inst1|temp[21] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.693 ns                ;
; 1.019 ns                                ; Restricted to 275.03 MHz ( period = 3.64 ns )       ; DC_block:inst1|temp[2]  ; DC_block:inst1|temp[17] ; clk        ; clk      ; 4.000 ns                    ; 3.701 ns                  ; 2.682 ns                ;