freq2.tan.rpt

一个基于quartus2的等精度频率计的设计

Timing Analyzer report for freq2
Mon Jul 09 11:00:29 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'fpgaclk'
  7. Clock Hold: 'clk'
  8. Clock Hold: 'fpgaclk'
  9. tsu
 10. tco
 11. tpd
 12. th
 13. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                ;
+------------------------------+----------+----------------------------------+------------------------------------------------+-------------------------+-------------------------+------------+----------+--------------+
; Type                         ; Slack    ; Required Time                    ; Actual Time                                    ; From                    ; To                      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+----------+----------------------------------+------------------------------------------------+-------------------------+-------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A      ; None                             ; 0.114 ns                                       ; Gate                    ; inst4                   ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A      ; None                             ; 18.123 ns                                      ; BZ_block:inst3|temp[6]  ; OUT[6]                  ; fpgaclk    ; --       ; 0            ;
; Worst-case tpd               ; N/A      ; None                             ; 16.292 ns                                      ; Sel[1]                  ; OUT[2]                  ; --         ; --       ; 0            ;
; Worst-case th                ; N/A      ; None                             ; -0.062 ns                                      ; Gate                    ; inst4                   ; --         ; clk      ; 0            ;
; Clock Setup: 'fpgaclk'       ; 0.509 ns ; 250.00 MHz ( period = 4.000 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; BZ_block:inst3|temp[3]  ; BZ_block:inst3|temp[22] ; fpgaclk    ; fpgaclk  ; 0            ;
; Clock Setup: 'clk'           ; 0.860 ns ; 250.00 MHz ( period = 4.000 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DC_block:inst1|temp[3]  ; DC_block:inst1|temp[22] ; clk        ; clk      ; 0            ;
; Clock Hold: 'fpgaclk'        ; 0.718 ns ; 250.00 MHz ( period = 4.000 ns ) ; N/A                                            ; BZ_block:inst3|temp[23] ; BZ_block:inst3|temp[23] ; fpgaclk    ; fpgaclk  ; 0            ;
; Clock Hold: 'clk'            ; 1.057 ns ; 250.00 MHz ( period = 4.000 ns ) ; N/A                                            ; DC_block:inst1|temp[23] ; DC_block:inst1|temp[23] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;          ;                                  ;                                                ;                         ;                         ;            ;          ; 0            ;
+------------------------------+----------+----------------------------------+------------------------------------------------+-------------------------+-------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;