dc_count.v

一个基于quartus2的等精度频率计的设计

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

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// Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
// Created on Sat Jul 07 09:48:23 2007

//  Module Declaration
module DC_Count
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	DC_CLK, DC_EN, CLR, DC_Count
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input DC_CLK;
	input DC_EN;
	input CLR;
	output [23:0] DC_Count;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg [23:0] temp;

initial
	begin
		temp = 0;
	end
	
always @(posedge DC_CLK)
	begin
		if(!CLR)
			begin
				temp <= temp+1;
			end
		else temp <= 0;
	end

assign DC_Count = (EN)? temp : 24'bz;

endmodule