📄 freq2.map.rpt
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; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 103 ;
; -- Combinational with no register ; 51 ;
; -- Register only ; 1 ;
; -- Combinational with a register ; 51 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 24 ;
; -- 3 input functions ; 17 ;
; -- 2 input functions ; 57 ;
; -- 1 input functions ; 4 ;
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 56 ;
; -- arithmetic mode ; 47 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 49 ;
; ; ;
; Total registers ; 52 ;
; Total logic cells in carry chains ; 50 ;
; I/O pins ; 15 ;
; Maximum fan-out node ; clr ;
; Maximum fan-out ; 67 ;
; Total fan-out ; 423 ;
; Average fan-out ; 3.58 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------+
; |freq2 ; 103 (1) ; 52 ; 0 ; 0 ; 15 ; 0 ; 51 (0) ; 1 (1) ; 51 (0) ; 50 (0) ; 0 (0) ; |freq2 ;
; |BZ_block:inst3| ; 24 (24) ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (24) ; 23 (23) ; 0 (0) ; |freq2|BZ_block:inst3 ;
; |Calculater:inst2| ; 50 (50) ; 0 ; 0 ; 0 ; 0 ; 0 ; 50 (50) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |freq2|Calculater:inst2 ;
; |DC_block:inst1| ; 24 (24) ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (24) ; 23 (23) ; 0 (0) ; |freq2|DC_block:inst1 ;
; |M8:inst| ; 4 (0) ; 3 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 3 (0) ; 4 (0) ; 0 (0) ; |freq2|M8:inst ;
; |lpm_counter:lpm_counter_component| ; 4 (0) ; 3 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 3 (0) ; 4 (0) ; 0 (0) ; |freq2|M8:inst|lpm_counter:lpm_counter_component ;
; |cntr_0sh:auto_generated| ; 4 (4) ; 3 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 3 (3) ; 4 (4) ; 0 (0) ; |freq2|M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 52 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 49 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 48 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 14:1 ; 8 bits ; 72 LEs ; 64 LEs ; 8 LEs ; No ; |freq2|Calculater:inst2|Selector0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: M8:inst|lpm_counter:lpm_counter_component ;
+------------------------+-------------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 3 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; cntr_0sh ; Untyped ;
+------------------------+-------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Jul 09 11:00:18 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freq2 -c freq2
Info: Found 1 design units, including 1 entities, in source file BZ_block.v
Info: Found entity 1: BZ_block
Info: Found 1 design units, including 1 entities, in source file Calculater.v
Info: Found entity 1: Calculater
Info: Found 1 design units, including 1 entities, in source file DC_block.v
Info: Found entity 1: DC_block
Info: Found 1 design units, including 1 entities, in source file M8.tdf
Info: Found entity 1: M8
Info: Found 1 design units, including 1 entities, in source file freq2.bdf
Info: Found entity 1: freq2
Info: Elaborating entity "freq2" for the top level hierarchy
Info: Elaborating entity "Calculater" for hierarchy "Calculater:inst2"
Warning (10235): Verilog HDL Always Construct warning at Calculater.v(42): variable "Data1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at Calculater.v(43): variable "Data1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at Calculater.v(44): variable "Data1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at Calculater.v(46): variable "Data2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at Calculater.v(47): variable "Data2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at Calculater.v(48): variable "Data2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Elaborating entity "BZ_block" for hierarchy "BZ_block:inst3"
Info: Elaborating entity "M8" for hierarchy "M8:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "M8:inst|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "M8:inst|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_0sh.tdf
Info: Found entity 1: cntr_0sh
Info: Elaborating entity "cntr_0sh" for hierarchy "M8:inst|lpm_counter:lpm_counter_component|cntr_0sh:auto_generated"
Info: Elaborating entity "DC_block" for hierarchy "DC_block:inst1"
Info: Implemented 118 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 8 output pins
Info: Implemented 103 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Processing ended: Mon Jul 09 11:00:20 2007
Info: Elapsed time: 00:00:02
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