config.help

ahb sdram interface.arm cpu series,include controller

  Say Y here to enable the Memory Management Unit.

MMU split icache/dcache table lookaside buffer
CONFIG_MMU_COMBINED
  Select "combined" for a combined icache/dcache table lookaside buffer,
  "split" for a split icache/dcache table lookaside buffer

MMU tlb replacement scheme
CONFIG_MMU_REPARRAY
  Select "LRU" to use the "least recently used" algorithm for TLB
  replacement, or "Increment" for a simple incremental replacement
  scheme.

Combined i/dcache tlb
CONFIG_MMU_I2
  Select the number of entries for the instruction TLB, or the
  combined icache/dcache TLB if such is used.

Split tlb, dcache
CONFIG_MMU_D2
  Select the number of entries for the dcache TLB.

DSU enable
CONFIG_DSU_ENABLE
  The debug support unit (DSU) allows non-intrusive debugging and tracing
  of both executed instructions and AHB transfers. If you want to enable
  the DSU, say Y here and select the configuration below.

Trace buffer enable
CONFIG_DSU_TRACEBUF
  Say Y to enable the trace buffer. The buffer is not necessary for
  debugging, only for tracing instructions and data transfers.

Enable instruction tracing
CONFIG_DSU_ITRACE
  If you say Y here, an instruction trace buffer will be implemented
  in each processor. The trace buffer will trace executed instructions
  and their results, and place them in a circular buffer. The buffer 
  can be read out by any AHB master, and in particular by the debug 
  communication link.

Size of trace buffer
CONFIG_DSU_ITRACESZ1
  Select the buffer size (in kbytes) for the instruction trace buffer. 
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
  need 2 kbyte.

Enable AHB tracing
CONFIG_DSU_ATRACE
  If you say Y here, an AHB trace buffer will be implemented in the
  debug support unit processor. The AHB buffer will trace all transfers
  on the AHB bus and save them in a circular buffer. The trace buffer 
  can be read out by any AHB master, and in particular by the debug 
  communication link.

Size of trace buffer
CONFIG_DSU_ATRACESZ1
  Select the buffer size (in kbytes) for the AHB trace buffer. 
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
  need 2 kbyte.


IU assembly printing
CONFIG_IU_DISAS
  Enable printing of executed instructions to the console.

IU assembly printing in netlist
CONFIG_IU_DISAS_NET
  Enable printing of executed instructions to the console also
  when simulating a netlist. NOTE: with this option enabled, it
  will not be possible to pass place&route.

32-bit program counters
CONFIG_DEBUG_PC32
  Since the LSB 2 bits of the program counters always are zero, they are
  normally not implemented. If you say Y here, the program counters will
  be implemented with full 32 bits, making debugging of the VHDL model
  much easier. Turn of this option for synthesis or you will be wasting
  area.

CONFIG_AHB_DEFMST
  Sets the default AHB master (see AMBA 2.0 specification for definition).
  Should not be set to a value larger than the number of AHB masters - 1.
  For highest processor performance, leave it at 0.

Default AHB master
CONFIG_AHB_RROBIN
  Say Y here to enable round-robin arbitration of the AHB bus. A N will
  select fixed priority, with the master with the highest bus index having
  the highest priority.

Support AHB split-transactions
CONFIG_AHB_SPLIT
  Say Y here to enable AHB split-transaction support in the AHB arbiter.
  Unless you actually have an AHB slave that can generate AHB split
  responses, say N and save some gates.

Default AHB master
CONFIG_AHB_IOADDR
  Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined 
  in the plug&play extentions of the AMBA bus. Should be kept to FFF 
  unless you really know what you are doing.

APB bridge address          
CONFIG_APB_HADDR
  Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
  kept at 800 for software compatibility. 


DSU enable
CONFIG_DSU_UART
  Say Y to enable the AHB uart (serial-to-AHB). This is the most
  commonly used debug communication link.

JTAG Enable
CONFIG_DSU_JTAG
  Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done 
  with GRMON through the boards JTAG chain at speed of 300 kbits/s. 
  Supported JTAG cables are Xilinx Parallel Cable III and IV.  

PROM/SRAM memory controller
CONFIG_SRCTRL
  Say Y here to enable a simple (and small) PROM/SRAM memory controller.
  The controller has a fixed number of waitstates, and is primarily
  intended for FPGA implementations. The RAM data bus is always 32 bits,
  the PROM can be configured to either 8 or 32 bits (hardwired).

8-bit memory support
CONFIG_SRCTRL_8BIT
  If you say Y here, the simple PROM/SRAM memory controller will
  implement 8-bit PROM mode.

PROM waitstates
CONFIG_SRCTRL_PROMWS
  Select the number of waitstates for PROM access.

RAM waitstates
CONFIG_SRCTRL_RAMWS
  Select the number of waitstates for RAM access.

IO waitstates
CONFIG_SRCTRL_IOWS
  Select the number of waitstates for IO access.

Read-modify-write support
CONFIG_SRCTRL_RMW
  Say Y here to perform byte- and half-word writes as a
  read-modify-write sequence. This is necessary if your
  SRAM does not have individual byte enables. If you are
  unsure, it is safe to say Y.

SRAM bank select
CONFIG_SRCTRL_SRBANKS
  Select number of SRAM banks.

SRAM bank size select
CONFIG_SRCTRL_BANKSZ
  Select size of SRAM banks in kBytes.

PROM address bit select
CONFIG_SRCTRL_ROMASEL
  Select address bit for PROM bank decoding.
Leon2 memory controller
CONFIG_MCTRL_LEON2
  Say Y here to enable the LEON2 memory controller. The controller
  can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
  and SRAM is programmable to 8-, 16- or 32-bits.

8-bit memory support
CONFIG_MCTRL_8BIT
  If you say Y here, the PROM/SRAM memory controller will support
  8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
  Say N to save a few hundred gates.

16-bit memory support
CONFIG_MCTRL_16BIT
  If you say Y here, the PROM/SRAM memory controller will support
  16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
  Say N to save a few hundred gates.

Write strobe feedback
CONFIG_MCTRL_WFB
  If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
  be used to enable the data bus drivers during write cycles. This
  will guarantee that the data is still valid on the rising edge of
  the write strobe. If you say N, the write strobes and the data bus
  drivers will be clocked on the rising edge, potentially creating
  a hold time problem in external memory or I/O. However, in all
  practical cases, there is enough capacitance in the data bus lines
  to keep the value stable for a few (many?) nano-seconds after the
  buffers have been disabled, making it safe to say N and remove a 
  combinational path in the netlist that might be difficult to 
  analyze.

Write strobe feedback
CONFIG_MCTRL_5CS
  If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
  be enabled. If you don't intend to use it, say N and save some gates.

SDRAM controller enable
CONFIG_MCTRL_SDRAM
  Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
  intend to use SDRAM, say N and save about 1 kgates.

SDRAM controller inverted clock
CONFIG_MCTRL_SDRAM_INVCLK
  If you say Y here, the SDRAM controller output signals will be delayed
  with 1/2 clock in respect to the SDRAM clock. This will allow the used
  of an SDRAM clock which in not strictly in phase with the internal 
  clock. This option will limit the SDRAM frequency to 40 - 50 MHz.

  On FPGA targets without SDRAM clock synchronizations through PLL/DLL, 
  say Y. On ASIC targets, say N and tell your foundry to balance the 
  SDRAM clock output.

SDRAM separate address buses
CONFIG_MCTRL_SDRAM_SEPBUS
  Say Y here if your SDRAM is connected through separate address
  and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
  board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.

64-bit data bus
CONFIG_MCTRL_SDRAM_BUS64
  Say Y here to enable 64-bit SDRAM data bus.

On-chip rom
CONFIG_AHBROM_ENABLE
  Say Y here to add a block on on-chip rom to the AHB bus. The ram
  provides 0-waitstates read access,  burst support, and 8-, 16- 
  and 32-bit data size. The rom will be syntheised into block rams
  on Xilinx and Altera FPGA devices, and into gates on ASIC 
  technologies. GRLIB includes a utility to automatically create
  the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
  documentation for details.

On-chip rom address
CONFIG_AHBROM_START
  Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
  a 1 Mbyte slot at the selected address. Default is 000, corresponding
  to AHB address 0x00000000. When address 0x0 is selected, the rom area
  of any other memory controller is set to 0x10000000 to avoid conflicts.

Enable pipeline register for on-chip rom
CONFIG_AHBROM_PIPE
  Say Y here to add a data pipeline register to the on-chip rom.
  This should be done when the rom is implemenented in (ASIC) gates,
  or in logic cells on FPGAs. Do not use this option when the rom is
  implemented in block rams. If enabled, the rom will operate with 
  one waitstate.

On-chip ram
CONFIG_AHBRAM_ENABLE
  Say Y here to add a block on on-chip ram to the AHB bus. The ram
  provides 0-waitstates read access and 0/1 waitstates write access.
  All AHB burst types are supported, as well as 8-, 16- and 32-bit
  data size.

On-chip ram size
CONFIG_AHBRAM_SZ1
  Set the size of the on-chip AHB ram. The ram is infered/instantiated
  as four byte-wide ram slices to allow byte and half-word write
  accesses. It is therefore essential that the target package can
  infer byte-wide rams. This is currently supported on the generic,
  virtex, virtex2, proasic and axellerator targets.

On-chip ram address
CONFIG_AHBRAM_START
  Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
  a 1 Mbyte slot at the selected address. Default is A00, corresponding
  to AHB address 0xA0000000.

UART1 enable
CONFIG_UART1_ENABLE
  Say Y here to enable UART1, or the console UART. This is needed to
  get any print-out from LEON3 systems regardless of operating system.

UART1 FIFO
CONFIG_UA1_FIFO1
  The UART has configurable transmitt and receive FIFO's, which can
  be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
  maximum throughput.


LEON3 interrupt controller
CONFIG_IRQ3_ENABLE
  Say Y here to enable the LEON3 interrupt controller. This is needed
  if you want to be able to receive interrupts. Operating systems like
  Linux, RTEMS and eCos needs this option to be enabled. If you intend
  to use the Bare-C run-time and not use interrupts, you could disable
  the interrupt controller and save about 500 gates.

Timer module enable
CONFIG_GPT_ENABLE
  Say Y here to enable the Modular Timer Unit. The timer unit consists
  of one common scaler and up to 7 independent timers. The timer unit
  is needed for Linux, RTEMS, eCos and the Bare-C run-times.

Timer module enable
CONFIG_GPT_NTIM
  Set the number of timers in the timer unit (1 - 7).

Scaler width
CONFIG_GPT_SW
  Set the width if the common pre-scaler (2 - 16 bits). The scaler
  is used to divide the system clock down to 1 MHz, so 8 bits should
  be sufficient for most implementations (allows clocks up to 256 MHz).

Timer width
CONFIG_GPT_TW
  Set the width if the timers (2 - 32 bits). 32 bits is recommended
  for the Bare-C run-time, lower values (e.g. 16 bits) can work with
  RTEMS and Linux.

Timer Interrupt
CONFIG_GPT_IRQ
  Set the interrupt number for the first timer. Remaining timers will
  have incrementing interrupts, unless the separate-interrupts option
  below is disabled.

Watchdog enable
CONFIG_GPT_WDOGEN
  Say Y here to enable the watchdog functionality in the timer unit.

Watchdog time-out value
CONFIG_GPT_WDOG
  This value will be loaded in the watchdog timer at reset.

GPIO port
CONFIG_GRGPIO_ENABLE
  Say Y here to enable a general purpose I/O port. The port can be
  configured from 1 - 32 bits, whith each port signal individually
  programmable as input or output. The port signals can also serve
  as interrupt inputs.

GPIO port witdth
CONFIG_GRGPIO_WIDTH
  Number of bits in the I/O port. Must be in the range of 1 - 32.

GPIO interrupt mask
CONFIG_GRGPIO_IMASK
  The I/O port interrupt mask defines which bits in the I/O port
  should be able to create an interrupt. 

ATA interface enable
CONFIG_ATA_ENABLE
  Say Y here to enable the ATA interace from OpenCores. The core has one
  AHB slave interface for accessing all control registers. 

ATA register address
CONFIG_ATAIO
  The control registers of the ATA core occupy 256 byte, and are 
  mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting
  defines at which address in the I/O area the registers appear (HADDR[19:8]).

ATA interrupt
CONFIG_ATAIRQ
  Defines which interrupt number the ATA core will generate.

UART debugging
CONFIG_DEBUG_UART
  During simulation, the output from the UARTs is printed on the
  simulator console. Since the ratio between the system clock and
  UART baud-rate is quite high, simulating UART output will be very
  slow. If you say Y here, the UARTs will print a character as soon
  as it is stored in the transmitter data register. The transmitter
  ready flag will be permanently set, speeding up simulation. However,
  the output on the UART tx line will be garbled.  Has not impact on
  synthesis, but will cause the LEON test bench to fail.

FPU register tracing
CONFIG_DEBUG_FPURF
  If you say Y here, all writes to the floating-point unit register file
  will be printed on the simulator console.