📄 mcs51.txt
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MCS-51 Hardware and Software Memorandum
By: Wu,ChuiHong
===============================================================================
General Info
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Inner RAM: 00H..7FH(All Type), 80H..FFH(for 8052/8032/89C52.. Only)
Bit Units: In Inner RAM, Bit00H..Bit7FH=20H.0..2FH.7
In SFR , Bit80H..BitFFH=P0.0..
Work Regs: Use Inner RAM 00H..07H;08H..0FH;10H..17H;18H..1FH;Ctrled By:RS1,RS0
Sys Stack: In 00H..7FH(FFH), Pointed By:SP, Default SP=07 (Stack from 08H..)
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External RAM & Extended I/O Ports: 0000H..FFFFH
BUS:Data:D0..D7; Addr:A0..A15 in P0 & P2; Ctrl:RD(-),WR(-),ALE(+)
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Program & Const ROM: 0000H..FFFFH
Entry: Reset Int0 CTC0 Int1 CTC1 Serial CTC2
Addr : 0000H 0003H 000BH 0013H 001BH 0023H 002BH
BUS : Data:D0..D7, Addr:A0..A15, Ctrl:PSEN(-),EA(-),ALE(+)
-------------------------------------------------------------------------------
Reset Status:PC=0000H, All Ports=FFH for Input, All Ints=Disabled&Low_Priority
SP=07H,ACC=PSW=T0=T1=SCON=TCON=TMOD=SCON=PCON=IP=IE=00H,DPTR=0000H
Reset Signal:High(>10ms) to Low
-------------------------------------------------------------------------------
Working Cycle Time=12*Crystal_Cycle_Time
-------------------------------------------------------------------------------
Ports: P0,P1,P2,P3; P0=Genuine Input; P1,P2,P3=Pseudo Input
Input From Pin: after Setb; Input From Latch: Write or Read_Change_Write
Output: Strong Pull Low; P0 Need Outer PullUp; P1,P2,P3:Weak PullHigh
P0 Used as A0..A7; P2 Used as A8..A15, When Extention
P3 Used as SerialPort(RXD,TXD), Int0,Int1, T0,T1, WR,RD
===============================================================================
INSTRUCTIONS THAT AFFECT FLAG SETTINGS
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Instruction Flag Instruction Flag
-------------------------------------------------------------------------------
CY OV AC CY OV AC
-------------------------------------------------------------------------------
ADD x x x SETB C 1
ADDC x x x CLR C 0
SUBB x x x CPL C x
MUL 0 x ANL C,bit x
DIV 0 x ANL C,/bit x
DA x ORL C,bit x
RRC x ORL C,/bit x
RLC x MOV C,bit x
CJNE x
===============================================================================
8051 INSTRUCTION SET
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Mnemonic Byte Cyc Mnemonic Byte Cyc
-------------------------------------------------------------------------------
1.Arithmetic operations:
ADD A,@Ri 1 1 INC A 1 1
ADD A,Rn 1 1 INC @Ri 1 1
ADD A,direct 2 1 INC Rn 1 1
ADD A,#data 2 1 INC DPTR 1 1
ADDC A,@Ri 1 1 INC direct 2 1
ADDC A,Rn 1 1 DEC A 1 1
ADDC A,direct 2 1 DEC @Ri 1 1
ADDC A,#data 2 1 DEC Rn 1 1
SUBB A,@Ri 1 1 DEC direct 2 1
SUBB A,Rn 1 1 MUL AB 1 4
SUBB A,direct 2 1 DIV AB 1 4
SUBB A,#data 2 1 DA A 1 1
-------------------------------------------------------------------------------
2.Logical opreations:
ANL A,@Ri 1 1 XRL A,@Ri 1 1
ANL A,Rn 1 1 XRL A,Rn 1 1
ANL A,direct 2 1 XRL A,direct 2 1
ANL A,#data 2 1 XRL A,#data 2 1
ANL direct,A 2 1 XRL direct,A 2 1
ANL direct,#data 3 2 XRL direct,#data 3 2
ORL A,@Ri 1 1 CLR A 1 1
ORL A,Rn 1 1 CPL A 1 1
ORL A,direct 2 1 RL A 1 1
ORL A,#data 2 1 RLC A 1 1
ORL direct,A 2 1 RR A 1 1
ORL direct,#data 3 2 RRC A 1 1
SWAP A 1 1
-------------------------------------------------------------------------------
3.Data transfer:
MOV A,@Ri 1 1 MOV DPTR,#data16 3 2
MOV A,Rn 1 1 MOVC A,@A+DPTR 1 2
MOV A,direct 2 1 MOVC A,@A+PC 1 2
MOV A,#data 2 1 MOVX A,@Ri 1 2
MOV @Ri,A 1 1 MOVX A,@DPTR 1 2
MOV @Ri,direct 2 2 MOVX @Ri,A 1 2
MOV @Ri,#data 2 1 MOVX @DPTR,A 1 2
MOV Rn,A 1 1 PUSH direct 2 2
MOV Rn,direct 2 2 POP direct 2 2
MOV Rn,#data 2 1 XCH A,@Ri 1 1
MOV direct,A 2 1 XCH A,Rn 1 1
MOV direct,@Ri 2 2 XCH A,direct 2 1
MOV direct,Rn 2 2 XCHD A,@Ri 1 1
MOV direct,direct 3 2
MOV direct,#data 3 2
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4.Boolean variable manipulation:
CLR C 1 1 ANL C,bit 2 2
SETB C 1 1 ANL C,/bit 2 2
CPL C 1 1 ORL C,bit 2 2
CLR bit 2 1 ORL C,/bit 2 2
SETB bit 2 1 MOV C,bit 2 1
CPL bit 2 1 MOV bit,C 2 2
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5.Program and machine control:
NOP 1 1 JZ rel 2 2
RET 1 2 JNZ rel 2 2
RETI 1 2 JC rel 2 2
ACALL addr11 2 2 JNC rel 2 2
AJMP addr11 2 2 JB bit,rel 3 2
LCALL addr16 3 2 JNB bit,rel 3 2
LJMP addr16 3 2 JBC bit,rel 3 2
SJMP rel 2 2 CJNE A,direct,rel 3 2
JMP @A+DPTR 1 2 CJNE A,#data,rel 3 2
DJNZ Rn,rel 2 2 CJNE @Ri,#data,rel 3 2
DJNZ direct,rel 3 2 CJNE Rn,#data,rel 3 2
===============================================================================
SPECIAL FUNCTION REGISTER
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Register (MSB) (LSB) Byte
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Symbol b7 b6 b5 b4 b3 b2 b1 b0 Address
+-------------------------------------------------------+
P0 | P0.7 | P0.6 | P0.5 | P0.4 | P0.3 | P0.2 | P0.1 | P0.0 | 80H(128)
SP | | 81H(129)
DPL | | 82H(130)
DPH | | 83H(131)
PCON | SMOD | -- | -- | -- | GF1 | GF0 | PD | IDL | 87H(135)
TCON | TF1 | TR1 | TF0 | TR0 | IE1 | IT1 | IE0 | IT0 | 88H(136)
TMOD | GATE | C/T | M1 | M0 | GATE | C/T | M1 | M0 | 89H(137)
TL0 | | 8AH(138)
TL1 | | 8BH(139)
TH0 | | 8CH(140)
TH1 | | 8DH(141)
P1 | P1.7 | P1.6 | P1.5 | P1.4 | P1.3 | P1.2 | P1.1 | P1.0 | 90H(144)
SCON | SM0 | SM1 | SM2 | REN | TB8 | RB8 | TI | RI | 98H(152)
SBUF | | 99H(153)
P2 | P2.7 | P2.6 | P2.5 | P2.4 | P2.3 | P2.2 | P2.1 | P2.0 | 0A0H(208)
IE | EA | -- | ET2 | ES | ET1 | EX1 | ET0 | EX0 | 0A8H(168)
P3 | RD(-)| WR(-)| T1 | T0 | INT1 | INT0 | TXD | RXD | 0B0H(176)
IP | -- | -- | PT2 | PS | PT1 | PX1 | PT0 | PX0 | 0B8H(184)
T2CON | TF2 | EXF2 | RCLK | TCLK |EXEN2 | TR2 | C/T2 |CP/RL2| 0C8H(200)
RCAP2L | | 0CAH(202)
RCAP2H | | 0CBH(203)
TL2 | | 0CCH(204)
TH2 | | 0CDH(205)
PSW | CY | AC | F0 | RS0 | RS1 | OV | F1 | P | 0D0H(208)
ACC | ACC.7| ACC.6| ACC.5| ACC.4| ACC.3| ACC.2| ACC.1| ACC.0| 0E0H(224)
B | B.7 | B.6 | B.5 | B.4 | B.3 | B.2 | B.1 | B.0 | 0F0H(240)
+-------------------------------------------------------+
===============================================================================
8051/8031/8052/8032 PIN CONFIGURATION
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+------------------+
8052/8032 +T2 P1.0 | 1 40 | VCC
only ---T2EX P1.1 | 2 39 | P0.0 AD0
P1.2 | 3 38 | P0.1 AD1
P1.3 | 4 37 | P0.2 AD2
P1.4 | 5 36 | P0.3 AD3
P1.5 | 6 35 | P0.4 AD4
P1.6 | 7 34 | P0.5 AD5
P1.7 | 8 33 | P0.6 AD6
RST | 9 32 | P0.7 AD7
RXD P3.0 | 10 MCS-51 31 | EA VDD
TXD P3.1 | 11 30 | ALE
INT0 P3.2 | 12 29 | PSEN
INT1 P3.3 | 13 28 | P2.7 A15
T0 P3.4 | 14 27 | P2.6 A14
T1 P3.5 | 15 26 | P2.5 A13
WR P3.6 | 16 25 | P2.4 A12
RD P3.7 | 17 24 | P2.3 A11
XTAL2 | 18 23 | P2.2 A10
XTAL1 | 19 22 | P2.1 A9
VSS | 20 21 | P2.0 A8
+------------------+
===============================================================================
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