syslib.c

VxWorks下的PowerPC 824X系列CPU的bSP包！

/* sysLib.c - Wind River SBC8240/8245 board series system-dependent library */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,12dec01,pch  Add nullVme driver
01b,29oct01,g_h  Add support for MPC8245
01a,11may01,g_h  created
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c         - Intel 8250 UART driver 
    ppcDecTimer.c      - PowerPC decrementer timer library (system clock)
    eeprom.c           - EEPROM driver
    byteNvRam.c        - byte-oriented generic non-volatile RAM library
    pciConfigLib.c     - PCI configuration library
    pciAutoConfig.c    - PCI device auto-configuration library
    m8240Epic.c        - MPC8240 EPIC Interrupt Controller
    m8240AuxClk.c      - MPC8240 Aux Clock driver

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "usrLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"
#include "drv/pci/pciAutoConfigLib.h"
#include "wrSbc824x.h"

/* defines */

#define ZERO    0


/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */
    ((FLASH8_BASE & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512K | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH8_BASE & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW),

    /* I BAT 1 */
    ((FLASH64_BASE & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_4M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH64_BASE & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW),

    /* I BAT 2 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 3 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) |  _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 0 -- EUMB */
    ((EUMB_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((EUMB_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 1 - PCI prefetchable memory + non-prefetchable memory  = 256MB */
    ((CPU_PCI_MEM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_MEM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 2 - PCI IO space 0xfe000000 to 0xff000000 -- covers the config address and data regs too */
    ((CPU_PCI_IO_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_IO_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 3 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_CACHE_INHIBIT),
};

#ifdef INCLUDE_MMU
/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory      Page Table size
 * -------------------      ---------------
 *        8 Meg              64 K
 *       16 Meg             128 K
 *       32 Meg             256 K
 *       64 Meg             512 K
 *      128 Meg               1 Meg
 *  .               .
 *  .               .
 *  .               .
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
{
    {
	/* Vector Table and Interrupt Stack */
	(void *) LOCAL_MEM_LOCAL_ADRS,
	(void *) LOCAL_MEM_LOCAL_ADRS,
	RAM_LOW_ADRS,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
    },

    {
	/* Local SDRAM  */
	(void *) RAM_LOW_ADRS,
	(void *) RAM_LOW_ADRS,
	LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
    },

    {
	/* UART Reg */
	(void *) UART_BASE,
	(void *) UART_BASE,
	UART_LEN,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
	/* EEPROM */
	(void *) EEPROM_BASE,
	(void *) EEPROM_BASE,
	EEPROM_LEN,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
	/* User LED Reg */
	(void *) LED_BASE,
	(void *) LED_BASE,
	LED_LEN,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
	/* 8-bit flash */
	(void *) FLASH8_BASE,
	(void *) FLASH8_BASE,
	FLASH8_LEN,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
	/* 64-bit flash */
	(void *) FLASH64_BASE,
	(void *) FLASH64_BASE,
	FLASH64_LEN,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    }
};

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

#endif /* INCLUDE_MMU */

int    sysCpu      = CPU;               /* system CPU type */
char * sysBootLine = BOOT_LINE_ADRS;    /* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;      /* catastrophic message area */
int    sysProcNum  = 0;				    /* processor number of this CPU */
int    sysFlags;                        /* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];    /* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];    /* name of file from which we booted */

/* locals */
LOCAL char sysModelStr[80];
LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG; 

/* forward declarations */

void	sysCpuCheck (void);
char *  sysPhysMemTop (void);

/* externals */

IMPORT UCHAR  sysInByte (ULONG);
IMPORT void   sysOutByte (ULONG, UCHAR);
IMPORT STATUS sysMemProbeSup (int length, char * src, char * dest);
IMPORT STATUS sysPciInit (void);
IMPORT void   sysClearBATsInvalidateTLBs (void);
 
/* BSP DRIVERS */
#ifdef INCLUDE_AUX_CLK
#include "m8240AuxClk.c"
#endif /* INCLUDE_AUX_CLK */

#ifdef INCLUDE_PCI
#include "sysPci.c"
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_PCI_AUTOCONF
#include "sysPciAutoConfig.c"
#endif /* INCLUDE_PCI_AUTOCONF */

#include "vme/nullVme.c"
#include "sysSerial.c"
#include "timer/ppcDecTimer.c" /* PPC603 & 604 have on chip timers */
#include "sysCacheLockLib.c"

#if (NV_RAM_SIZE == NONE)
#include "mem/nullNvRam.c"
#else
#include "eeprom.c"
#include "mem/byteNvRam.c"
#endif

#include "m8240.h"
#include "m8240Epic.c"

/* network driver */
#ifdef INCLUDE_NETWORK
	#ifdef INCLUDE_END
		#ifdef INCLUDE_FEI82557END
			#include "sysFei82557End.c"
		#endif /* INCLUDE_FEI82557END */
		#ifdef INCLUDE_PNIC169END
			#include "sysPnic169End.c"
		#endif /* INCLUDE_PNIC169END */
	#endif /* INCLUDE_END */
#include "sysNet.c"
#endif /* INCLUDE_NETWORK */

#ifdef INCLUDE_VWARE_LAUNCH
#include "sysVware.c"
#endif /* INCLUDE_VWARE_LAUNCH */

/***********************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.  
*
* RETURNS: A pointer to the string.
*/

char * sysModel 
    ( 
    void
    )
    {
    UINT cpu;
    char cpuStr[80];

    /* Determine CPU type and build display string */
    cpu = CPU_TYPE;

    switch (cpu)
        {
        case CPU_TYPE_8240:
            sprintf(cpuStr, "8240");
            break;
        case CPU_TYPE_8245:
            sprintf(cpuStr, "8245");
            break;
        default:
            sprintf (cpuStr, "xxx");
            break;
        }

    sprintf (sysModelStr, "MPC%s -- Wind River BSP. SBC%s Board", cpuStr, cpuStr);

    return (sysModelStr);

    }

/***********************************************************************
*