wrsbc824x.h

VxWorks下的PowerPC 824X系列CPU的bSP包！

/* wrSbc824x.h - board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01d,01apr02,kab  Add missing sysPci* decls
01c,27oct01,g_h rename to wrSbc824x.h and add support for 8245
01b,11may01,g_h rename to wrSbc8240.h
01a,15aug98,est	adopted from templatePpc/config.h
*/

/*
This file contains I/O addresses and related constants for the board.
*/

#ifndef	INCwrSbc824xh
#define	INCwrSbc824xh

#ifdef __cplusplus
extern "C" {
#endif

/* include Motorola MC8240 definitions */
#include "vxWorks.h"
#include "m8240.h"

/* On board device I/O adress */         

#define EUMB    	        0xfcf00000  
#define EUMB_BASE_ADRS 	        EUMB
#define EUMB_LEN    	        0x00080000  
#define EUMB_REG_SIZE	        EUMB_LEN
#define FLASH64_BASE 	        0xff000000 /* 64Bit FLASH base address */
#define FLASH64_LEN 	        0x00400000 /* 4MB 64Bit FLASH */
#define FLASH8_BASE 	        0xfff00000 /* 8Bit FLASH/SRAM base address */
#define FLASH8_LEN 	        0x00080000 /* 512KB 8Bit FLASH/SRAM */
#define EEPROM_BASE 	        0xffe00000 /* 8Bit EEPROM base address */
#define EEPROM_LEN 	        0x00002000 /* 8KB 8Bit EEPROM */
#define UART_BASE 	        0xfff80000 /* UART base address */
#define UART_LEN 	        0x00001000 /* UART size */
#define LED_BASE                0xffe80000 /* LED base address */
#define LED_LEN 	        0x00001000 /* LED size */
#define COM1_BASE_ADR		0xfff80000 /* serial port 1 */

/* Clock Parameters */

#define	SYS_CLK_RATE_MIN        10   /* min system clock rate    */
#define	SYS_CLK_RATE_MAX        5000 /* max system clock rate    */
#define	AUX_CLK_RATE_MIN        4    /* min auxiliary clock rate */
#define	AUX_CLK_RATE_MAX        5000 /* max auxiliary clock rate */

/* interrupt vector definitions */

#define INT_VEC_IRQ0	        0x00 /* vector for IRQ0 */
#define INT_NUM_IRQ0            INT_VEC_IRQ0

/* interrupt signal/level assignments */

#undef  COM1_INT_LVL
#define COM1_INT_LVL	        3
#define PCI_SLOT_J3_INT_LVL     0
#define PCI_SLOT_J2_INT_LVL     1

/* interrupt vectors */

#undef  COM1_INT_VEC
#define COM1_INT_VEC            INT_VEC_EXT_IRQ3
#define PCI_SLOT_J3_INT_VEC     INT_VEC_EXT_IRQ0
#define PCI_SLOT_J2_INT_VEC     INT_VEC_EXT_IRQ1

/*
 * PCI part
 */

#define MPC8240_PCI_BRIDGE      0

#define PCI_SLOT_J3             0x10
#define PCI_SLOT_J2             0x11

#define PCI_INTA_IRQ            0
#define PCI_INTB_IRQ            1

#define PCI8240_PRIMARY_CAR     0xFEC00CF8 /* PCI config address register */
#define PCI8240_PRIMARY_CDR     0xFEE00CFC /* PCI config data    register */

/* MC8240 Memory Map B */

#define PCIMEM                  0x80000000 /* PCI Mem Space 0x8000 0000 - 0xFE00 0000 */
#define PCIIO                   0xFE000000 /* PCI Mem Space 0xFE00 0000 - 0xFEC0 0000 */
#define PCICAR                  0xFE000000 /* PCI CAR Reg   0xFEC0 0000 - 0xFEE0 0000 */
#define PCICDR                  0xFE000000 /* PCI CDR Reg   0xFEE0 0000 - 0xFEF0 0000 */
#define PCIIACK                 0xFE000000 /* PCI IACK Reg  0xFEF0 0000 - 0xFF00 0000 */

/* PCI I/O function defines */

#define INT_NUM_IRQ0            INT_VEC_IRQ0

/* PCI CONFIG_ADDR & CONFIG_DATA */

#define PCI_MSTR_CNFG_ADRS      0xfec00000  
#define PCI_MSTR_CNFG_ADRS_B    0xfec00000  
#define PCI_MSTR_CFNG_SIZE_B    0x00300000 /* 3MB for CHRP map */
#define PCI_MSTR_CFNG_SIZE      PCI_MSTR_CFNG_SIZE_B  

/* PCI IO space */

#define PCI_MSTR_IO_LOCAL       0xfe800000  
#define PCI_MSTR_IO_LOCAL_B     0xfe800000  
#define PCI_MSTR_IO_SIZE        0x00100000 /* 1MB (Adjusted) */
#define PCI_MSTR_IO_BUS	        0x00800000 /* PCI bus view */

/* PCI IACK space (read to generate PCI IACK) */

#define PCI_MSTR_IACK_LOCAL     0xfef00000  
#define PCI_MSTR_IACK_LOCAL_B	0xfef00000  
#define PCI_MSTR_IACK_SIZE	VM_PAGE_SIZE  		/* for MMU */

/* PCI (non-prefetchable) memory space */

#define PCI_MSTR_MEMIO_LOCAL	0x00000000  
#define PCI_MSTR_MEMIO_LOCAL_B	0x00000000  
#define PCI_MSTR_MEMIO_SIZE	0x01000000 
#define PCI_MSTR_MEMIO_BUS	0x80000000
#define PCI_MSTR_MEMIO_BUS_B	0x80000000

/* Slave window that makes local (60x bus) memory visible to PCI devices */

#define PCI_SLV_MEM_LOCAL	0x80000000
#define PCI_SLV_MEM_LOCAL_A	0x80000000
#define PCI_SLV_MEM_LOCAL_B	0x00000000	
#define PCI_SLV_MEM_SIZE	LOCAL_MEM_SIZE	

/* PCI (non-prefetchable) memory adrs to CPU (60x bus) adrs */

#define PCI_MEMIO2LOCAL(x) ((int)(x))

/*
 * Address range definitions for PCI bus.
 * Used with vxMemProbe() hook sysBusProbe().
 */

#define IS_PCI_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)PCIMEM) && \
((UINT32)(adrs) < (UINT32)PCIIO))

/* Latency Timer value - 64 PCI clocks */

#undef  PCI_LAT_TIMER  
#define PCI_LAT_TIMER           0x40

#define CPU_PCI_MEM_ADRS	0x80000000  /* 32 bit prefetchable memory base addres of PCI mem */
#define CPU_PCI_MEM_SIZE	0x08000000  /* 32 bit prefetchable memory size  */
#define CPU_PCI_NO_PRE_MEM_ADRS	0x88000000  /* 32 bit non-prefetchable memory location */
#define CPU_PCI_NO_PRE_MEM_SIZE	0x08000000  /* 32 bit non-prefetchable memory size */
#define CPU_PCI_IO_ADRS	        0xFE000000  /* base addres of PCI IO */
#define CPU_PCI_IO_SIZE	        0x01000000  

/* PCI device configuration definitions */
#ifndef PCI_CFG_FORCE
#    define PCI_CFG_FORCE	0x0     /* UNSUPPORTED */
#endif

#ifndef PCI_CFG_AUTO
#     define PCI_CFG_AUTO	0x1	/* IS SUPPORTED */
#endif
        
#ifndef PCI_CFG_NONE
#    define PCI_CFG_NONE	0x2	/* UNSUPPORTED */
#endif

/* PCI configuration type */

#define PCI_CFG_TYPE		PCI_CFG_AUTO 

#ifndef _ASMLANGUAGE

#ifndef PCI_IN_BYTE
#   define PCI_IN_BYTE(x)       sysPciInByte (x)
    IMPORT  UINT8               sysPciInByte  (UINT32 address);
#endif

#ifndef PCI_IN_WORD
#   define PCI_IN_WORD(x)       sysPciInWord (x)
    IMPORT  UINT16              sysPciInWord  (UINT32 address);
#endif

#ifndef PCI_IN_LONG
#   define PCI_IN_LONG(x)       sysPciInLong (x)
    IMPORT  UINT32              sysPciInLong  (UINT32 address);
#endif

#ifndef PCI_OUT_BYTE
#   define PCI_OUT_BYTE(x,y)    sysPciOutByte (x,y)
    IMPORT  void                sysPciOutByte (UINT32 address, UINT8  data);
#endif

#ifndef PCI_OUT_WORD
#   define PCI_OUT_WORD(x,y)    sysPciOutWord (x,y)
    IMPORT  void                sysPciOutWord (UINT32 address, UINT16 data);
#endif

#ifndef PCI_OUT_LONG
#   define PCI_OUT_LONG(x,y)    sysPciOutLong (x,y)
    IMPORT  void                sysPciOutLong (UINT32 address, UINT32 data);
#endif

#define PCI_MAX_BUS		1 	 
#define PCI_MAX_DEV		18
#define PCI_MAX_FUNC		8

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 32 32-bit value = 128 bytes */

#define PCI_CLINE_SZ		0x20

/* Memory Bus Rate in Hertz */

#undef  MEMORY_BUS_SPEED
#undef  DEC_CLOCK_FREQ  
#undef	DEC_CLK_TO_INC	

#ifdef  BUS_SPEED_100MHZ
#define MEMORY_BUS_SPEED        (100 * 1000000)
#define DEC_CLOCK_FREQ          (100000000)
#define	DEC_CLK_TO_INC	        4
#else  /* 66 MHZ */
#define MEMORY_BUS_SPEED        (67 * 1000000) 
#define DEC_CLOCK_FREQ          (66666667) 
#define	DEC_CLK_TO_INC	        4	
#endif

/*
 * This macro returns the positive difference between two unsigned ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)	        (abs((int)a - (int)b))

#define UART_REG_ADDR_INTERVAL  1 /* addr diff of adjacent regs */

/* Define CPU type and number of Serial channels  */

#define BUS                       0      /* bus-less board            */
#define CPU                       PPC603 /* CPU type                  */
#define N_SIO_CHANNELS            1      /* No. serial I/O channels   */

/* create a single macro INCLUDE_MMU */

#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
#define INCLUDE_MMU
#endif

/* Only one can be selected, FULL overrides BASIC */

#ifdef INCLUDE_MMU_FULL
#   undef INCLUDE_MMU_BASIC
#endif

#define WRONG_CPU_MSG "Unsupported processor type for this board.\n";

#define CPU_TYPE                ((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_8240           0x81    /* PPC 8240 CPU */
#define CPU_TYPE_8245           0x8081    /* PPC 8240 CPU */

/* General */

/* Common I/O synchronizing instructions */

#undef  EIEIO
#define EIEIO                   WRS_ASM("	eieio")

#undef  EIEIO_SYNC
#define EIEIO_SYNC              WRS_ASM("	eieio;	sync")

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif	/* INCwrSbc824x */