rominit.s

VxWorks下的PowerPC 824X系列CPU的bSP包！

/* romInit.s - Wind River SBC8240 ROM initialization module */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,17dec01,kab  fix for diab
01a,11may01,g_h  created
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

This code is intended to be generic across PowerPC 603/604 boards.
Hardware that requires special register setting or memory
mapping to be done immediately, may do so here.
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"	
#include "wrSbc824x.h"

        /* defines */
#define ORCR32(reg,val) \
	 lis	   r3,0x8000;\
	 ori	   r3,r3,reg;\
	 stwbrx    r3,0,r4;\
	 sync             ;\
	 lwbrx     r6,0,r5;\
	 lis	   r3,HI(val);\
	 ori	   r3,r3,LO(val);\
	 or	   r3,r3,r6;\
	 stwbrx    r3,0,r5;\
	 sync

#define  OUTCR32(reg,val)\
         lis     r3,0x8000;\
         ori     r3,r3,LO(reg);\
         stwbrx  r3,0,r4;\
	 sync             ;\
         lis     r3,HI(val);\
         ori     r3,r3,LO(val);\
         stwbrx  r3,0,r5;\
	 sync

#define  OUTCR16(reg,val)\
         lis     r3,0x8000;\
         ori     r3,r3,LO(reg);\
         rlwinm  r6,r3,0,30,31;\
         rlwinm  r3,r3,0,0,29;\
         stwbrx  r3,r0,r4;\
	 sync            ;\
         li      r3,LO(val);\
         sthbrx  r3,r6,r5;\
	 sync

	
#define  OUTCR8(reg,val)\
         lis     r3,0x8000;\
         ori     r3,r3,LO(reg);\
         rlwinm  r6,r3,0,30,31;\
         rlwinm  r3,r3,0,0,29;\
         stwbrx  r3,r0,r4;\
	 sync            ;\
         li      r3,LO(val);\
         stbx    r3,r6,r5;\
	 sync

	/* Exported internal functions */

	FUNC_EXPORT(_romInit)	/* start of system code */
	FUNC_EXPORT(romInit)	/* start of system code */

	/* externals */

	FUNC_IMPORT(romStart)	/* system initialization routine */

        _WRS_TEXT_SEG_START

/***************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* SYNOPSIS
* \ss
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
* \se
*/

FUNC_BEGIN(_romInit)
FUNC_BEGIN(romInit)

	bl	cold
        nop                     /* pad to 8 byte boundary */
	bl	warm

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-2001 Wind River Systems, Inc."
	.align 2

cold:

        bl      romInit824x		/* 8240 specific initialation */

	li	r24, BOOT_COLD
	bl	start			/* skip over next instruction */

			
warm:
	or	r24, r3, r3		/* startType to r24 */

start:
	/* Zero-out registers: r0 & SPRGs */

	xor     r0,r0,r0
	mtspr   272,r0
	mtspr   273,r0
	mtspr   274,r0
	mtspr   275,r0

        /* initialize the stack pointer */

        lis     sp, HI(STACK_ADRS)
        ori     sp, sp, LO(STACK_ADRS)

	/*
	 *	Set MPU/MSR to a known state
	 *	Turn on FP
	 */

	andi.	r3, r3, 0
	ori	r3, r3, _PPC_MSR_FP
	sync
	mtmsr 	r3
	isync

	/* Init the floating point control/status register */

	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync

	/* Initialize the floating point data regsiters to a known state */

	bl	ifpdr_value
	.long	0x3f800000	/* 1.0 */
ifpdr_value:
	mfspr	r3,8
	lfs	f0,0(r3)
	lfs	f1,0(r3)
	lfs	f2,0(r3)
	lfs	f3,0(r3)
	lfs	f4,0(r3)
	lfs	f5,0(r3)
	lfs	f6,0(r3)
	lfs	f7,0(r3)
	lfs	f8,0(r3)
	lfs	f9,0(r3)
	lfs	f10,0(r3)
	lfs	f11,0(r3)
	lfs	f12,0(r3)
	lfs	f13,0(r3)
	lfs	f14,0(r3)
	lfs	f15,0(r3)
	lfs	f16,0(r3)
	lfs	f17,0(r3)
	lfs	f18,0(r3)
	lfs	f19,0(r3)
	lfs	f20,0(r3)
	lfs	f21,0(r3)
	lfs	f22,0(r3)
	lfs	f23,0(r3)
	lfs	f24,0(r3)
	lfs	f25,0(r3)
	lfs	f26,0(r3)
	lfs	f27,0(r3)
	lfs	f28,0(r3)
	lfs	f29,0(r3)
	lfs	f30,0(r3)
	lfs	f31,0(r3)
	sync

	/*
	 *	Set MPU/MSR to a known state
	 *	Turn off FP
	 */

	andi.	r3, r3, 0
	sync
	mtmsr 	r3
	isync

	/* Init the Segment registers */

	andi.	r3, r3, 0
	isync
	mtsr    0,r3
	isync
	mtsr    1,r3
	isync
	mtsr    2,r3
	isync
	mtsr    3,r3
	isync
	mtsr    4,r3
	isync
	mtsr    5,r3
	isync
	mtsr    6,r3
	isync
	mtsr    7,r3
	isync
	mtsr    8,r3
	isync
	mtsr    9,r3
	isync
	mtsr    10,r3
	isync
	mtsr    11,r3
	isync
	mtsr    12,r3
	isync
	mtsr    13,r3
	isync
	mtsr    14,r3
	isync
	mtsr    15,r3
	isync

	/* Turn off data and instruction cache control bits */
	
	mfspr	r3,HID0			/* r3 = HID0 */
	andi.	r3,r3,0xcfff		/* make sure lock bits are clear */
	ori	r4,r3,(_PPC_HID0_ICE | _PPC_HID0_DCE | _PPC_HID0_ICFI | _PPC_HID0_DCFI)		
                                        /* r4 has ICE,DCE,ICI,DCI bits set */
	andi.	r3,r3,0x03ff		/* r3 has enable bits cleared */
	sync
	mtspr	HID0,r4			/* HIDO = r4 */
	isync
	sync
	mtspr	HID0,r3			/* HIDO = r3 */
	isync

	bl	romMinimumBATsInit
	bl	romInvalidateTLBs

	/* turn the Instruction cache ON for faster FLASH ROM boots */

#ifdef USER_I_CACHE_ENABLE 
	ori	r3, r3, 0x8000		/* set ICE bit */

        /*
         * The setting of the instruction cache enable (ICE) bit must be
         * preceded by an isync instruction to prevent the cache from being
         * enabled or disabled while an instruction access is in progress.
         */
	isync
        mtspr   HID0, r3
#endif

	/* go to C entry point */
	
        or	r3, r24, r24		/* Restore startType */
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */
        lis     r6, HI(romStart)
        ori	r6, r6, LO(romStart)
        lis     r7, HI(romInit)
        ori	r7, r7, LO(romInit)
        lis     r8, HI(ROM_TEXT_ADRS)
        ori	r8, r8, LO(ROM_TEXT_ADRS)
	sub	r6, r6, r7
	add	r6, r6, r8 
	mtlr	r6
	blr
FUNC_END(romInit)
FUNC_END(_romInit)

/***************************************************************************
*
* romInit824x - MPC8240 specific initialation
*
* This routine do the MPC8240 specific initialation
*
* SYNOPSIS
* \ss
* void romInit824x
*     (
*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romInit824x)
        /* 
         * OUTCrx macros used below require 
         * r4 & r5 are already loaded with the values below 
         *
         * r4 = 0xfec00000 
         * r5 = 0xfee00000
         */
        lis  r4,0xfec0
        lis  r5,0xfee0

        OUTCR16(0x04,0x0006)     /* PCI command */
        OUTCR16(0x06,0xffff)     /* PCI status */
        OUTCR16(0x46,0xc000)     /* PCI Arbiter Control */

        OUTCR16(0x70,0x0000)     /* PWRMNG1 */
        OUTCR16(0x72,0xf740)     /* PWRMNG2 AND ODCR */
        OUTCR16(0x74,0x1400)     /* CLKDCR */
        OUTCR32(0x78,EUMB)       /* EUMBBAR */
        OUTCR8(0xc0,0x0001)      /* ERRENA1 */
        OUTCR8(0xc1,0x00ff)      /* ERRDET1 */
        OUTCR8(0xc3,0x0000)      /* 60XBERR */
        OUTCR8(0xc4,0x0000)      /* ERRENA2 */
        OUTCR8(0xc5,0x00ff)      /* ERRDET2 */
        OUTCR8(0xc7,0x0000)      /* PCIBERR */
        OUTCR32(0xc8,0x00000000) /* BERRADDR */
        OUTCR32(0xe0,0x00000040) /* AMBOR */

        /* 
         * Let's do the mem registers that aren't different
         * for various bus speeds and RAM sizes first
         */
        OUTCR32(0x84,0xffffffff)  /* SMEMADD2 */
        OUTCR32(0x8c,0x03030303)  /* EXTSMEM2 */
        OUTCR32(0x9c,0x03030303)  /* EXTEMEM2 */
        OUTCR32(0x94,0xffffffff)  /* EMEMADD2 */
	
#if (defined(BUS_SPEED_100MHZ) || !defined(BUS_SPEED_66MHZ))
        OUTCR32(0x80,0xffffff00)  /* SMEMADD1 */
        OUTCR32(0x88,0x03030300)  /* EXTSMEM1 */
        OUTCR32(0x98,0x03030300)  /* EXTEMEM1 */
  #if (defined(INCLUDE_64MEG_SDRAM) || !defined(INCLUDE_16MEG_SDRAM))
        OUTCR32(0x90,0xffffff3f)  /* EMEMADD1 */
        OUTCR32(0xf0,0xfff00000)  /* MEMCTRL1 */
  #else
        OUTCR32(0x90,0xffffff0f)  /* EMEMADD1 */
        OUTCR32(0xf0,0xfff00003)  /* MEMCTRL1 */
  #endif /* INCLUDE_64MEG_SDRAM || INCLUDE_16MEG_SDRAM */
        OUTCR8(0xa3,0x0000)       /* MEMPMODE */
        OUTCR8(0xa0,0x0001)       /* MEMBNKEN (1 64Meg Bank) */

        OUTCR32(0xf4,0x00000312)  /* MEMCTRL2 */
        OUTCR32(0xf8,0x03300000)  /* MEMCTRL3 */
        OUTCR32(0xfc,0x37302230)  /* MEMCTRL4 */
        ORCR32(0xa8,0x00001800)   /* PCIR1 */

    	sync
        sync
	sync
	isync

        ORCR32(0xf0,0x00080000)   /* MEMCTRL1 */
	
	sync
	sync
	sync
	isync
#else /* BUS_SPEED_66MHZ */

	/* 66MHz *implies* presence of the old 2-bank memory */
        OUTCR32(0x80,0xffff0800)  /* SMEMADD1 */
        OUTCR32(0x88,0x03030000)  /* EXTSMEM1 */
        OUTCR32(0x90,0xffff0f07)  /* EMEMADD1 */
        OUTCR32(0x98,0x03030000)  /* EXTEMEM1 */
        OUTCR8(0xa0,0x0003)       /* MEMBNKEN (2 8Meg Banks) */
        OUTCR8(0xa3,0x007a)       /* MEMPMODE */
        OUTCR32(0xf4,0x0000020c)  /* MEMCTRL2 */
        OUTCR32(0xf8,0xf2300000)  /* MEMCTRL3 */
        OUTCR32(0xfc,0x25302220)  /* MEMCTRL4 */
        OUTCR32(0xf0,0xffb8000f)  /* MEMCTRL1 */
        OUTCR32(0xa8,0xff041c08)  /* PCIR1 */
        OUTCR32(0xac,0x00000000)  /* PCIR2 */

#endif /* BUS_SPEED_XXMHZ */
FUNC_END(romInit824x)

/***************************************************************************
*
* romInvalidateTLBs - invalidate the TLB's.
*
* This routine will invalidate the TLB's.
*
* SYNOPSIS
* \ss
* void romInvalidateTLBs
*     (
*     void
*     )
* \se
*
* SEE ALSO: romClearBATs(), romMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(romInvalidateTLBs)
	isync
	/* invalidate entries within both TLBs */
	li	r3,128
	mtctr	r3		/* CTR = 32  */
	xor	r3,r3,r3	/* r3 = 0    */
	isync			/* context sync req'd before tlbie */
tlbloop:
	tlbie	r3
	addi	r3,r3,0x1000	/* increment bits 15-19 */
	sync			/* sync instr req'd after tlbie      */
	bdnz	tlbloop		/* decrement CTR, branch if CTR != 0 */
	blr
FUNC_END(romInvalidateTLBs)

/***************************************************************************
*
* romMinimumBATsInit - initialize the minimum BAT's
*
* This routine will initialize the minimum BAT's register, and terun MMU on.
*
* SYNOPSIS
* \ss
* void romMinimumBATsInit
*     (
*     void
*     )
* \se
*
* NOTE: When the MMU is disabled, the processor is said to be in Real Addressing 
*       Mode. In this mode, all memory accesses are governed by a default set of 
*       bit values for the WIMG attribute bits. For data accesses, the default 
*       WIMG = 0011 and for instruction fetches default WIMG=0001. In both cases, 
*       the guarded (G) bit is set and the cache-inhibit (I) bit is clear. In 
*       other words, in real addressing mode, the entire address space of the 
*       processor is cacheable ("NOT cache-inhibited") and guarded -- independent 
*       of whether the caches are enabled or not.
*
*       The guarded attribute merely prevents out-of-order and speculative 
*       *loads*. More details are avalible in section 5.2.1.5 of the PowerPC 
*       programming environments manual for a more complete explanation of the 
*       guarded attribute. While guarded is a necessary condition for those 
*       memory spaces in which devices reside, it is not a sufficient condition. 
*       Memory accesses to devices must be both guarded and cache inhibited. 
*       Physically disabling the data cache does not provide this second, 
*       equally necessary, condition.
*
*       Above, I used the term "NOT cache-inhibited" to draw attention to an 
*       important distinction between cache-inhibited memory accesses and 
*       cacheable memory accesses that are made while the cache itself is 
*       disabled. A naive interpretation of "cacheability" holds that these two 
*       concepts are equivalent -- they are not. To prevent out-of-order 
*       *stores* to devices, we must mark the memory addresses at which those 
*       devices reside as cache inhibited. The only way to do this is to enable 
*       the MMU. So it holds that in order to enforce in-order loads AND stores, 
*       we must enable the MMU and mark the appropriate memory regions as CI & G.
*
* SEE ALSO: romClearBATs(), romInvalidateTLBs()

* RETURNS: N/A
*/

FUNC_BEGIN(romMinimumBATsInit)

	lis     r3, HI(0x00000032)
	ori     r3, r3, LO(0x00000032)
	sync
	mtspr	DBAT0L,r3		
	isync

	lis     r3, HI(0x000007FF)	/* SDRAM (64M block) */ 
	ori     r3, r3, LO(0x000007FF)
	sync
	mtspr	DBAT0U,r3		
	isync

	lis     r3, HI(0xF000002A)		
	ori     r3, r3, LO(0xF000002A)
	sync
	mtspr	DBAT1L,r3		
	isync

	lis     r3, HI(0xF0001FFF)	/* Pheripherals (256M block) */
	ori     r3, r3, LO(0xF0001FFF)	/* (eeprom,serial,ictrl)    */
	sync				/* (PCI register space)     */
	mtspr	DBAT1U,r3		
	isync

	lis     r3, HI(0x8000002A)		
	ori     r3, r3, LO(0x8000002A)
	sync
	mtspr	DBAT2L,r3		
	isync

	lis     r3, HI(0x800001FF)	/* 0x80000000 (16M block) */
	ori     r3, r3, LO(0x800001FF)
	sync
	mtspr	DBAT2U,r3		
	isync

	/* Turn on Data Relocation */
	sync
	mfmsr	r3
	ori     r3, r3, _PPC_MSR_DR
	sync
	mtmsr   r3
	isync
	blr
FUNC_END(romMinimumBATsInit)