m8240.h

VxWorks下的PowerPC 824X系列CPU的bSP包！

/* m8240.h - Motorola 8240 CPU control registers */

/* Copyright 1994-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,24may99,wfg  written.
*/

/*
This file contains I/O addresses and related constants for the MC8240
*/

#ifndef __INCm8240h
#define __INCm8240h

#ifdef __cplusplus
extern "C" {
#endif

#ifndef	_ASMLANGUAGE

/* interrupt Vector/Priority masks */
#define EPIC_INT_MASK       0x80000000
#define EPIC_INT_ACT        0x40000000
#define EPIC_INT_POLARITY   0x00800000
#define EPIC_INT_SENSE      0x00400000

/* 8240 interrupt vector assignments */
#define INT_VEC_SPURIOUS   0xFF 
#define INT_VEC_EXT_IRQ0   0x20
#define INT_VEC_EXT_IRQ1   0x21
#define INT_VEC_EXT_IRQ2   0x22
#define INT_VEC_EXT_IRQ3   0x23
#define INT_VEC_EXT_IRQ4   0x24
#define INT_VEC_TIMER0     0x30
#define INT_VEC_TIMER1     0x31
#define INT_VEC_TIMER2     0x32
#define INT_VEC_TIMER3     0x33
#define INT_VEC_DMA0       0x40
#define INT_VEC_DMA1       0x41
#define INT_VEC_I2C        0x42
#define INT_VEC_I2O        0x43
/* 8240 interrupt priority assignments */
#define INT_PRI_EXT_IRQ0   (0x0e << 16)
#define INT_PRI_EXT_IRQ1   (0x0d << 16)
#define INT_PRI_EXT_IRQ2   (0x0c << 16)
#define INT_PRI_EXT_IRQ3   (0x0b << 16)
#define INT_PRI_EXT_IRQ4   (0x0a << 16)
#define INT_PRI_TIMER0     (0x09 << 16)
#define INT_PRI_TIMER1     (0x08 << 16)
#define INT_PRI_TIMER2     (0x07 << 16)
#define INT_PRI_TIMER3     (0x06 << 16)
#define INT_PRI_DMA0       (0x05 << 16)
#define INT_PRI_DMA1       (0x04 << 16)
#define INT_PRI_I2C        (0x03 << 16)
#define INT_PRI_I2O        (0x02 << 16)


/* MC8240 Emmbedded Utilities Base Address Register(EUMBBAR) offset */

#define M8240_EUMBBAR  0x0078  /* offest of EUMBBAR in PCI config space */


/* M8240 Embedded Programmable Interrupt Control registers */
#define EPIC_OFS	0x40000   /* offset of EPIC with EUMB */

#define M8240_EPIC_FEATURE(eumbbase)	((UINT32 *)(eumbbase+0x41000))  
#define M8240_EPIC_GCR(eumbbase)	((UINT32 *)(eumbbase+0x41020)) 
#define M8240_EPIC_EICR(eumbbase)	((UINT32 *)(eumbbase+0x41030)) 
#define M8240_EPIC_EPIC_ID(eumbbase)	((UINT32 *)(eumbbase+0x41080)) 
#define M8240_EPIC_PROC_IN(eumbbase)	((UINT32 *)(eumbbase+0x41090)) 
#define M8240_EPIC_S_VECTOR(eumbbase)	((UINT32 *)(eumbbase+0x410E0))
#define M8240_EPIC_TFREQ(eumbbase)	((UINT32 *)(eumbbase+0x410F0)) 
#define M8240_EPIC_GTCC0(eumbbase)	((UINT32 *)(eumbbase+0x41100)) 
#define M8240_EPIC_GTBC0(eumbbase)	((UINT32 *)(eumbbase+0x41110))
#define M8240_EPIC_GTVR0(eumbbase)	((UINT32 *)(eumbbase+0x41120)) 
#define M8240_EPIC_GTD0(eumbbase)	((UINT32 *)(eumbbase+0x41130))  
#define M8240_EPIC_GTCC1(eumbbase)	((UINT32 *)(eumbbase+0x41140)) 
#define M8240_EPIC_GTBC1(eumbbase)	((UINT32 *)(eumbbase+0x41150)) 
#define M8240_EPIC_GTVR1(eumbbase)	((UINT32 *)(eumbbase+0x41160)) 
#define M8240_EPIC_GTD1(eumbbase)	((UINT32 *)(eumbbase+0x41170)) 
#define M8240_EPIC_GTCC2(eumbbase)	((UINT32 *)(eumbbase+0x41180))  
#define M8240_EPIC_GTBC2(eumbbase)	((UINT32 *)(eumbbase+0x41190))  
#define M8240_EPIC_GTVR2(eumbbase)	((UINT32 *)(eumbbase+0x411A0))  
#define M8240_EPIC_GTD2(eumbbase)	((UINT32 *)(eumbbase+0x411B0))  
#define M8240_EPIC_GTCC3(eumbbase)	((UINT32 *)(eumbbase+0x411C0))  
#define M8240_EPIC_GTBC3(eumbbase)	((UINT32 *)(eumbbase+0x411D0))  
#define M8240_EPIC_GTVR3(eumbbase)	((UINT32 *)(eumbbase+0x411E0))  
#define M8240_EPIC_GTD3(eumbbase)	((UINT32 *)(eumbbase+0x411F0))  
#define M8240_EPIC_EISVP0(eumbbase)	((UINT32 *)(eumbbase+0x50200)) 
#define M8240_EPIC_EISD0(eumbbase)	((UINT32 *)(eumbbase+0x50210))  
#define M8240_EPIC_EISVP1(eumbbase)	((UINT32 *)(eumbbase+0x50220)) 
#define M8240_EPIC_EISD1(eumbbase)	((UINT32 *)(eumbbase+0x50230))  
#define M8240_EPIC_EISVP2(eumbbase)	((UINT32 *)(eumbbase+0x50240)) 
#define M8240_EPIC_EISD2(eumbbase)	((UINT32 *)(eumbbase+0x50250))  
#define M8240_EPIC_EISVP3(eumbbase)	((UINT32 *)(eumbbase+0x50260)) 
#define M8240_EPIC_EISD3(eumbbase)	((UINT32 *)(eumbbase+0x50270))  
#define M8240_EPIC_EISVP4(eumbbase)	((UINT32 *)(eumbbase+0x50280)) 
#define M8240_EPIC_EISD4(eumbbase)	((UINT32 *)(eumbbase+0x50290))  
#define M8240_EPIC_SISVP0(eumbbase)	((UINT32 *)(eumbbase+0x50200)) 
#define M8240_EPIC_SISD0(eumbbase)	((UINT32 *)(eumbbase+0x50210))  
#define M8240_EPIC_SISVP1(eumbbase)	((UINT32 *)(eumbbase+0x50220))  
#define M8240_EPIC_SISD1(eumbbase)	((UINT32 *)(eumbbase+0x50230))  
#define M8240_EPIC_SISVP2(eumbbase)	((UINT32 *)(eumbbase+0x50240)) 
#define M8240_EPIC_SISD2(eumbbase)	((UINT32 *)(eumbbase+0x50250)) 
#define M8240_EPIC_SISVP3(eumbbase)	((UINT32 *)(eumbbase+0x50260))  
#define M8240_EPIC_SISD3(eumbbase)	((UINT32 *)(eumbbase+0x50270))  
#define M8240_EPIC_SISVP4(eumbbase)	((UINT32 *)(eumbbase+0x50280)) 
#define M8240_EPIC_SISD4(eumbbase)	((UINT32 *)(eumbbase+0x50290))  
#define M8240_EPIC_SISVP5(eumbbase)	((UINT32 *)(eumbbase+0x502A0)) 
#define M8240_EPIC_SISD5(eumbbase)	((UINT32 *)(eumbbase+0x502B0)) 
#define M8240_EPIC_SISVP6(eumbbase)	((UINT32 *)(eumbbase+0x502C0)) 
#define M8240_EPIC_SISD6(eumbbase)	((UINT32 *)(eumbbase+0x502D0)) 
#define M8240_EPIC_SISVP7(eumbbase)	((UINT32 *)(eumbbase+0x502E0))  
#define M8240_EPIC_SISD7(eumbbase)	((UINT32 *)(eumbbase+0x502F0))  
#define M8240_EPIC_SISVP8(eumbbase)	((UINT32 *)(eumbbase+0x50300)) 
#define M8240_EPIC_SISD8(eumbbase)	((UINT32 *)(eumbbase+0x50310)) 
#define M8240_EPIC_SISVP9(eumbbase)	((UINT32 *)(eumbbase+0x50320)) 
#define M8240_EPIC_SISD9(eumbbase)	((UINT32 *)(eumbbase+0x50330)) 
#define M8240_EPIC_SISVP10(eumbbase)	((UINT32 *)(eumbbase+0x50340)) 
#define M8240_EPIC_SISD10(eumbbase)	((UINT32 *)(eumbbase+0x50350)) 
#define M8240_EPIC_SISVP11(eumbbase)	((UINT32 *)(eumbbase+0x50360)) 
#define M8240_EPIC_SISD11(eumbbase)	((UINT32 *)(eumbbase+0x50370))  
#define M8240_EPIC_SISVP12(eumbbase)	((UINT32 *)(eumbbase+0x50380))  
#define M8240_EPIC_SISD12(eumbbase)	((UINT32 *)(eumbbase+0x50390)) 
#define M8240_EPIC_SISVP13(eumbbase)	((UINT32 *)(eumbbase+0x503A0)) 
#define M8240_EPIC_SISD13(eumbbase)	((UINT32 *)(eumbbase+0x503B0))  
#define M8240_EPIC_SISVP14(eumbbase)	((UINT32 *)(eumbbase+0x503C0)) 
#define M8240_EPIC_SISD14(eumbbase)	((UINT32 *)(eumbbase+0x503D0)) 
#define M8240_EPIC_SISVP15(eumbbase)	((UINT32 *)(eumbbase+0x503E0))  
#define M8240_EPIC_SISD15(eumbbase)	((UINT32 *)(eumbbase+0x503F0)) 
#define M8240_EPIC_I2C_VR(eumbbase)	((UINT32 *)(eumbbase+0x51020)) 
#define M8240_EPIC_I2C_DR(eumbbase)	((UINT32 *)(eumbbase+0x51030)) 
#define M8240_EPIC_DMA0_VR(eumbbase)	((UINT32 *)(eumbbase+0x51040)) 
#define M8240_EPIC_DMA0_DR(eumbbase)	((UINT32 *)(eumbbase+0x51050)) 
#define M8240_EPIC_DMA1_VR(eumbbase)	((UINT32 *)(eumbbase+0x51060)) 
#define M8240_EPIC_DMA1_DR(eumbbase)	((UINT32 *)(eumbbase+0x51070)) 
#define M8240_EPIC_I2O_VR(eumbbase)	((UINT32 *)(eumbbase+0x510C0)) 
#define M8240_EPIC_I2O_DR(eumbbase)	((UINT32 *)(eumbbase+0x510D0)) 
#define M8240_EPIC_PCTP(eumbbase)	((UINT32 *)(eumbbase+0x60080))  
#define M8240_EPIC_PIACK(eumbbase)	((UINT32 *)(eumbbase+0x600A0)) 
#define M8240_EPIC_PEOI(eumbbase)	((UINT32 *)(eumbbase+0x600B0))

#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCm8240h */