target.nr

VxWorks下的PowerPC 824X系列CPU的bSP包！

    i8250Sio.c             - Intel 8250 UART driver 
    ppcDecTimer.c          - PowerPC decrementer timer library (system clock)
    byteNvRam.c            - byte-oriented generic non-volatile RAM library
    pciConfigLib.c         - PCI configuration library
    pciAutoConfig.c        - PCI device auto-configuration library
    pciConfigShow.c        - Show routines of PCI bus library
    m8240Epic.c -          - MPC8240 EPIC Interrupt Controller
    m8240AuxClk.c -        - MPC8240 Aux clock driver
    pnic169End.obj         - 10baseT/100baseTX PNIC 169 Ethernet driver
    fei82557End.o          - 10baseT/100baseTX FEI 82557/9 Ethernet driver
.CE
.PP
The BSP configures UART to implement a console device and the FEI 82557 as an 
Ethernet.

.SS "Support for L1 Cache Locking"
L1 cache locking is available for MPC8240/8245. The cache lock routine can be
used to lock the entire data or instruction cache with a specified memory region. 

.SS "Default Memory Map"
.CS
        Memory Map from CPU point of view

Start               Size         Access to
-----------------------------------------------------
0x0                 64MB (min)   SDRAM DIMM
0xFF000000	     4MB         On Board FLASH
0xFFF00000	   512K          On Board FLASH or SRAM (Configured by jumper)
0xFFE00000           8K          EEPROM
0xFFF80000           8Bit        UART
.CE

.SS "Shared Memory"
NA

.SS "66Mhz/100Mhz Bus Speed"
This BSP supports both 66Mhz and 100Mhz 8240/8245 Bus Speeds. The bus
speed is a conditionally compiled BSP parameter.  A #define, in the
"config.h" file, is used to specify the desired bus speed.
.CS
  /* Bus Speed */
  #define  BUS_SPEED_100MHZ  /* Option BUS_SPEED_100MHZ or BUS_SPEED_66MHZ */
.CE

Note: Hardware jumpers PLL_CFG0..4 determine the bus and core speeds for the 
      board. Consult the SBC8240/8245 Evaluation Board Users' Manual for 
      details.

.SS "SDRAM Size"
.PP
Initial boards and bsps were supplied with a 16Meg SDRAM
DIMM; more recent evaluation boards are supplied with a 64Meg DIMM.
the BSP is logically setup for 64Meg of SDRAM. The 64Meg is divided 
into two halves. The first 32Meg is useable for code and data. 
The second 32Meg is specified as USER_RESERVED_MEM memory. The 64Meg 
option is specified as a #define in the "config.h" file. If your 
board comes with 16Meg of SDRAM follow those steps:

1. Change the following macro in "config.h":

From:
.CS
   #define INCLUDE_64MEG_SDRAM
   #undef  INCLUDE_16MEG_SDRAM			    
.CE
To:
.CS
   #undef  INCLUDE_64MEG_SDRAM
   #define INCLUDE_16MEG_SDRAM			    
.CE

2. Change the following line in the Makefile:

From:
.CS
        RAM_HIGH_ADRS   = 01F00000
.CE

To:
.CS
        RAM_HIGH_ADRS   = 00E00000
.CE

3. Re build the bootrom, and re create the vxWorks bootable project.

The reason the BSP divides the 64Meg SDRAM into two 32Meg sections has 
to do with the EABI compilation option of a 24 bit address. The default
compilation options generates a 'bl' for branch instructions. This 
increases performance, but places a 32Meg address limit on the code.
  
There are two "work around" to this limitation.
 
	1.) recompile all the source with the -mlongcall compilation flag
	2.) add remaining 32Meg to the memory pool vi the memAddToPool() 
            function.
  
Option #1 would require all the libraries, driver, and the BSP to be 
recompiled with the -mlongcall compiler option. This results in a number
of code changes; the most obvious code change is branches are implemented
via brlr instruction verses the bl instruction.
  
Option #2, the preferable options, requires the USER_RESERVED_MEM and the
memAddToPool() constructs be used to specify the remaining 32Meg to be added
to the memory pool. Consult WindTech Note WTN41 for details on specifying
user memory.

.SS "Network Configuration"
All boards have comes with PCI Ethernet card which is 10baseT and 100baseTX
compatible. The Ethernet card uses an RJ45 (twisted pair) jack and can be 
used with either 10baseT or 100baseTX. The Ethernet driver automatically 
senses and configures the port as 10baseT or 100baseTX.

.SS "Switching between the FEI82557 to PNIC169"
The BSP is using by default the FEI driver, but it is supporting also the PNIC
driver that is used for the NetGear card. Please follow those steps to get the
BSP working with the PNIC driver instead of the FEI:

    1. In "config.h" change the following lines:

       FROM:
.CS
       #define BOOT_DEVICE FEI_END
.CE
       TO:
.CS
       #define BOOT_DEVICE PNIC_END
.CE

    2. In the makefile change the following lines:

       FROM:
.CS
       MACH_EXTRA    = #pnic169End.obj 
.CE
       TO:
.CS
       MACH_EXTRA    = pnic169End.obj
.CE

    3. Now reduild the bootrom and create a new VxWorks image project and 
       build it.

** Don't forget to change the device name to "pnic" in the "boot device" line 
   in the bootrom.

.SS " NVRAM Support" 
This BSP implements NvRam via a EEPROM device. There are a few user 
parameters associated with this device. The parameters are located in
the "config.h" file and are:
.CS  
	#undef  INCLUDE_EEPROM_LOCKING
	#define SMART_EEPROM_WRITE
.CE
 
The INCLUDE_EEPROM_LOCKING parameter is typically #undef'ed. If #define'ed, the
EEPROM will be software locked between accesses. This was implemented on the
BSP to work around a power-on EEPROM corruption problem. It should be noted, 
that if the EEPROM is locked, its contents can not be altered via an emulator 
or visionPROBE II or visionICE II (JTAG does not meet the minimum timing 
relationships needed).

The SMART_EEPROM_WRITE parameter is typically #define'd. When defined, the 
EEPROM write code first checks to see if a cell is the desired value. If the 
memory location already contains the desired value, the write is skipped. This 
was implemented to increase the life of the EEPROM device.
  
.SS "Ethernet Address"
The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the INTEL82557/9/0 chip. The Ethernet address should be 
writen on the card itself, 12 digit number in Hex format. If it's not writen on 
the card, you can use the "arp -a" command from the host command line in order 
to get the card Ethernet address.

.SS "BOOT FLASH"
The BSP configures to use the 512KByte On Board Flash. This is the only flash 
that can be used for bootrom.

.SS "Serial Configuration"
The UART is configured as UART devices with 8 data bits, 1 stop
bit, hardware handshaking, and parity disabled.

.SS "Serial Connections"
This VxWorks SBC8240/8245 BSP uses a simple 3 wire connection and standard 
phone jacks where pin 1 = RIN, pin 2 = TOUT, pin 3 = NC, and pin 4 = GND.

.SS "SCSI Configuration"
There is no SCSI interface on this board.

.SS "Network Configuration"
10/100Mb/s Fast Ethernet port, the BSP can be used with one of the two NIC
Intel 82557/9 or NetGear FA310 (PNIC169). The BSP support use of nly one NIC 
at a time.

.SS "VME Access"
NA

.SS "PCI Access"
Two 32-bit address, 32-bit data; complies with PCI Local Bus Specification, 
Revision 2.1 The MPC8240/8245 have PCI bridge inside.

.SS "ROM Considerations"
bootrom_uncmp is provided with this BSP. The bootrom is configured to 
a ROM base address of 0x0. When programing the bootrom to the FLASH an offset
of 0xFFF00100 need to be given, also it's configured to use the 8 MByte on 
board Flash ROM and the 100/10BaseT Intel 82557/9 PCI Ethernet card as default 
boot device and the RS232 as console device.


.SS "Delivered Objects"
The following images are delivered with the wrSbc824x BSP:

.IP
bootrom_uncmp
.IP
bootrom_uncmp.hex
.IP
bootrom
.IP
bootrom.hex
.IP
vxWorks
.IP
vxWorks.st
.IP
pnic169End.obj
.LP

.SS "Make Targets"
Only bootrom_uncmp, bootrom, vxWorks have been tested.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information that the user needs
to know about the BSP.

.SS "Known Problems"

.SS "Problem with the polling mode and the PNIC Ethernet driver"
The current version of the Ethernet driver is not supporting polling mode, this 
cause the system debug mode option not to work when using the CroseWind 
debuger.

SH "BIBLIOGRAPHY"
.iB "Embedded Support Tools SBC8240 Hardware Reference Manual"
.iB "Motorola MPC8240 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC Microprocessor Family: The Programming Environments,"
.iB "DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual,"
.iB "Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1,"
.iB "PCI to PCI Bridge Architecture Specification 2.0,"