mpc107.h

PowerPC 74XX系列CPU的VxWorks BSP源代码！

/* mpc107.h - MPC107 register numbers and values  */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1998 Motorola, Inc. */

/*
modification history
--------------------
01c,21jan02,pcs  Add PPMC8245_ID
01b,12sep00,ksn  updated to support SP755 and SP7400 (teamF1).
01a,10oct99,mtl  written from SPS/Motorola by teamF1
*/

#ifndef	__INCmpc107h
#define	__INCmpc107h

#ifdef __cplusplus
extern "C" {
#endif

/* defines */

/* MPC107 device and vendor ID's */

#define MPC107_DEV_VEN_ID       0x1057       /* vendor for Motorola */    
#define PCI_DEV_ID_8240         0x00031057   /* Vendor & Dev Id for Kahlua */
#define PPMC8245_ID         0x00061057   /* Vendor & Dev Id for Kahlua */
#define PCI_DEV_ID_MPC107	0x00041057   /* Vendor & Dev Id for mpc107 */
#define	MPC107_DEV_ID		PCI_DEV_ID_MPC107

#ifdef SP8240
#undef	MPC107_DEV_ID
#define MPC107_DEV_ID		PCI_DEV_ID_8240
#endif
    
/* MPC107 configuration adrs and data register for map A & B */

#define MPC107_CFG_ADDR_PREP	0x80000cf8   /* MPC107 cfg reg map A */
#define MPC107_CFG_DATA_PREP	0x80000cfc   /* MPC107 cfg data map A */
#define MPC107_CFG_ADDR_CHRP	0xfec00000   /* MPC107 cfg reg map B */
#define MPC107_CFG_DATA_CHRP	0xfee00000   /* MPC107 cfg data map B */
#define MPC107_PICR1_MAPB	0x0          /* PICR1 bit 16 map B */
#define MPC107_PICR1_MAPA	0x1          /* PICR1 bit 16 map A */

/* addresses */

/* MPC107 indirect configuration registers */

#define MPC107_CFG_BASE		0x80000000   /* Base adrs of cfg regs */
#define MPC107_CFG_BASE_16 	0x8000	     /* MPC107_CFG_BASE >> 16 */

#define MPC107_PCICMD_ADRS	(MPC107_CFG_BASE + 0x04)  /* PCI cmd reg */
#define MPC107_PCISTAT_ADRS	(MPC107_CFG_BASE + 0x06)  /* PCI status reg */
#define MPC107_ODCR_ADRS	(MPC107_CFG_BASE + 0x73)  /* out driver reg */
#define MPC107_EUMBBA_ADRS	(MPC107_CFG_BASE + 0x78)  /* Embedded Utilities
                                                           * Memory Block Base
                                                           * address */

#define EUMBBAR_VAL	        0x80500000	/* Base address of EUMBBAR */ 

#define MPC107_MSAR1_ADRS	(MPC107_CFG_BASE + 0x80)  /* MSAR1 */
#define MPC107_XMSAR1_ADRS	(MPC107_CFG_BASE + 0x88)  /* XMSAR1 */
#define MPC107_MEAR1_ADRS	(MPC107_CFG_BASE + 0x90)  /* MEAR1 */
#define MPC107_XMEAR1_ADRS	(MPC107_CFG_BASE + 0x98)  /* XMEAR1 */
#define MPC107_MSAR2_ADRS  	(MPC107_CFG_BASE + 0x84)  /* MSAR2 */
#define MPC107_XMSAR2_ADRS	(MPC107_CFG_BASE + 0x8c)  /* XMSAR2 */
#define MPC107_MEAR2_ADRS	(MPC107_CFG_BASE + 0x94)  /* MEAR2 */
#define MPC107_XMEAR2_ADRS	(MPC107_CFG_BASE + 0x9c)  /* XMEAR2 */
#define MPC107_MBER_ADRS	(MPC107_CFG_BASE + 0xa0)  /* MBER */
#define MPC107_MPMR_ADRS	(MPC107_CFG_BASE + 0xa3)  /* Page mode reg */

#define MPC107_PICR1_ADRS   	(MPC107_CFG_BASE + 0xa8)  /* PICR1 adrs */
#define MPC107_PICR2_ADRS   	(MPC107_CFG_BASE + 0xac)  /* PICR2 adrs */

#define MPC107_MCCR1_ADRS	(MPC107_CFG_BASE + 0xf0)  /* MCCR1 */
#define MPC107_MCCR2_ADRS 	(MPC107_CFG_BASE + 0xf4)  /* MCCR2 */
#define MPC107_MCCR3_ADRS   	(MPC107_CFG_BASE + 0xf8)  /* MCCR3 */
#define MPC107_MCCR4_ADRS   	(MPC107_CFG_BASE + 0xfc)  /* MCCR4 */

/* Default Settings & values */
/* Most hard coded settings are per SPS version of Sandpoint BSP */

#define MPC107_PCICMD_VAL	0x00000006	/* PCI COMMAND Default value */
#define MPC107_PICR1_VAL        0xff041b18	/* PICR1 (SP 8240) setting, TBEN/DEC etc. */
#define MPC107_PICR2_VAL        0x04040004	/* PICR2 (SP 8240) setting */
#define MPC107_FLASH_WRITE_BIT	(0x1 << 12)

/* High and low words of bit-mask of read-only bits in PICR1 */
#define MPC107_PICR1_ROBITS_16    0x0011  	/* Mask of Readonly bits */
#define MPC107_PICR1_ROBITS_00    0x0000  	/* Mask of Readonly bits */

/* 
 * initial values for the MPC107 SDRAM memory control registers.
 * Refer to MPC107 users manual and addendums for details on values.
 * These defaults are to support SDRAM on the PPMC8240
 */

#define MPC107_MCCR1_VAL	0x8800ffff
#define MPC107_MCCR2_VAL	0x000006b8   /* 33 MHZ - REFINT */
#define MPC107_MCCR3_VAL	0x78400000   /* DIMM CAS latency = 3,
                                              * REFREC = 0b1000 */
#define MPC107_MCCR4_VAL	0x35303239   /* PRETOACT = 3, ACTOPRE = 5,
                                              * REGISTERED buffers,
                                              * SDMODE=032, ACTORW= 3,
                                              * BSTOPRE(6-9)=9 */

/* Bitmasks to enable memory banks 0 - 7, used in config.h */

#define MPC107_BANK0_ENABLE	(0x1 << 0)	/* Enable BANK 0 */
#define MPC107_BANK1_ENABLE	(0x1 << 1)	/* Enable BANK 1 */
#define MPC107_BANK2_ENABLE	(0x1 << 2)	/* Enable BANK 2 */
#define MPC107_BANK3_ENABLE	(0x1 << 3)	/* Enable BANK 3 */
#define MPC107_BANK4_ENABLE	(0x1 << 4)	/* Enable BANK 4 */
#define MPC107_BANK5_ENABLE	(0x1 << 5)	/* Enable BANK 5 */
#define MPC107_BANK6_ENABLE	(0x1 << 6)	/* Enable BANK 6 */
#define MPC107_BANK7_ENABLE	(0x1 << 7)	/* Enable BANK 7 */

/* SDRAM Page mode register initial value. */

#define MPC107_MPMR_VAL	        0x0032	/* PPMC8240 SDRAM, 33Mhz w/ROMFAL =8 */

/* 
 * The macros MPC107_BANK[x]_ADRS indicate the starting addresses of 
 * each memory bank.   The default definitions provide for a contiguous 
 * and non-overlapping memory map for the eight banks regardless of the
 * defined size of each bank.  
 *
 * The only configurable options are the BANK enables and the BANK
 * sizes which are fully configurable in config.h by the user.
 * Leave these settings alone.
 */

/* carve up a valid mapping based on config.h sizes */

#define MPC107_BANK0_ADRS	0x00000000	/* Mem starts at 0x0 */
#define MPC107_BANK1_ADRS	(MPC107_BANK0_ADRS + MPC107_BANK0_SIZE)	
#define MPC107_BANK2_ADRS	(MPC107_BANK1_ADRS + MPC107_BANK1_SIZE)	
#define MPC107_BANK3_ADRS	(MPC107_BANK2_ADRS + MPC107_BANK2_SIZE)	
#define MPC107_BANK4_ADRS	(MPC107_BANK3_ADRS + MPC107_BANK3_SIZE)	
#define MPC107_BANK5_ADRS	(MPC107_BANK4_ADRS + MPC107_BANK4_SIZE)	
#define MPC107_BANK6_ADRS	(MPC107_BANK5_ADRS + MPC107_BANK5_SIZE)	
#define MPC107_BANK7_ADRS	(MPC107_BANK6_ADRS + MPC107_BANK6_SIZE)	
#define MPC107_BANK7_ADRS_END	((MPC107_BANK7_ADRS + MPC107_BANK7_SIZE) - 1)

/* break down the mapping addresses into MPC107 register settings */

#define START_BANK0		(((MPC107_BANK0_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK0		(((MPC107_BANK1_ADRS - 1) >> 20) & (0x3ff))
#define START_BANK1		(((MPC107_BANK1_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK1		(((MPC107_BANK2_ADRS - 1) >> 20) & (0x3ff))
#define START_BANK2		(((MPC107_BANK2_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK2		(((MPC107_BANK3_ADRS - 1) >> 20) & (0x3ff))
#define START_BANK3		(((MPC107_BANK3_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK3		(((MPC107_BANK4_ADRS - 1) >> 20) & (0x3ff))
#define START_BANK4		(((MPC107_BANK4_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK4		(((MPC107_BANK5_ADRS - 1) >> 20) & (0x3ff))
#define START_BANK5		(((MPC107_BANK5_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK5		(((MPC107_BANK6_ADRS - 1) >> 20) & (0x3ff))
#define START_BANK6		(((MPC107_BANK6_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK6		(((MPC107_BANK7_ADRS - 1) >> 20) & (0x3ff))
#define START_BANK7		(((MPC107_BANK7_ADRS)     >> 20) & (0x3ff))
#define ENDOF_BANK7		(((MPC107_BANK7_ADRS_END) >> 20) & (0x3ff))

#define STMEM_MASK 		(0x0ff)	
#define XTMEM_MASK 		(0x003)

/* 
 * Setup the actual MPC107 register values.
 * These are currently used in romInit.s, sysLib.c, sysALib.s 
 */

/* memory starting address register one */

#define MPC107_MSAR1_VAL (((START_BANK0 & STMEM_MASK) << 0)  | \
			 ((START_BANK1 & STMEM_MASK) << 8)  | \
			 ((START_BANK2 & STMEM_MASK) << 16) | \
			 ((START_BANK3 & STMEM_MASK) << 24))

/* memory starting extended address register one */

#define MPC107_XMSAR1_VAL ((((START_BANK0 >> 8) & XTMEM_MASK) << 0)  | \
			  (((START_BANK1 >> 8) & XTMEM_MASK) << 8)  | \
			  (((START_BANK2 >> 8) & XTMEM_MASK) << 16) | \
			  (((START_BANK3 >> 8) & XTMEM_MASK) << 24))

/* memory ending address register one */

#define MPC107_MEAR1_VAL (((ENDOF_BANK0 & STMEM_MASK) << 0)  | \
			 ((ENDOF_BANK1 & STMEM_MASK) << 8)  | \
			 ((ENDOF_BANK2 & STMEM_MASK) << 16) | \
			 ((ENDOF_BANK3 & STMEM_MASK) << 24))

/* memory ending extended address register one */

#define MPC107_XMEAR1_VAL ((((ENDOF_BANK0 >> 8) & XTMEM_MASK) << 0)  | \
			  (((ENDOF_BANK1 >> 8) & XTMEM_MASK) << 8)  | \
			  (((ENDOF_BANK2 >> 8) & XTMEM_MASK) << 16) | \
			  (((ENDOF_BANK3 >> 8) & XTMEM_MASK) << 24))

/* memory starting address register two */

#define MPC107_MSAR2_VAL (((START_BANK4 & STMEM_MASK) << 0)  | \
			 ((START_BANK5 & STMEM_MASK) << 8)  | \
			 ((START_BANK6 & STMEM_MASK) << 16) | \
			 ((START_BANK7 & STMEM_MASK) << 24))

/* memory starting extended address register two */

#define MPC107_XMSAR2_VAL ((((START_BANK4 >> 8) & XTMEM_MASK) << 0)  | \
			  (((START_BANK5 >> 8) & XTMEM_MASK) << 8)  | \
			  (((START_BANK6 >> 8) & XTMEM_MASK) << 16) | \
			  (((START_BANK7 >> 8) & XTMEM_MASK) << 24))

/* memory ending address register two */

#define MPC107_MEAR2_VAL (((ENDOF_BANK4 & STMEM_MASK) <<  0) | \
			 ((ENDOF_BANK5 & STMEM_MASK) <<  8) | \
			 ((ENDOF_BANK6 & STMEM_MASK) << 16) | \
			 ((ENDOF_BANK7 & STMEM_MASK) << 24))

/* memory ending extended address register two */

#define MPC107_XMEAR2_VAL ((((ENDOF_BANK4 >> 8) & XTMEM_MASK) <<  0) | \
			  (((ENDOF_BANK5 >> 8) & XTMEM_MASK) <<  8) | \
			  (((ENDOF_BANK6 >> 8) & XTMEM_MASK) << 16) | \
			  (((ENDOF_BANK7 >> 8) & XTMEM_MASK) << 24))

#ifdef __cplusplus
}
#endif

#endif	/* __INCmpc107h */