syscachelockalib.s

PowerPC 74XX系列CPU的VxWorks BSP源代码！

/* sysCacheLockALib.s  - cache locking assembly routines */

/* Copyright 2000 Wind River, Inc */

/*
modification history
--------------------
01c,28mar02,pcs  Update use of FUNC_*
01b,08may01,pch  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)
01a,12dec00,ksn   created (teamf1)         
*/


/* includes */
        
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"        
#include "cacheLib.h"
#include "config.h"
#include "sysCacheLockLib.h"
#include "sysL2BackCache.h"
               
        /* globals */
        
        FUNC_EXPORT(_sysL1CacheLock)
        FUNC_EXPORT(_sysL1CacheUnlock)
        FUNC_EXPORT(SYSL1CACHELOCK_STARTADRS)
        FUNC_EXPORT(SYSL1CACHELOCK_ENDADRS)
#if defined(INCLUDE_CACHE_L2)        
        FUNC_EXPORT(_sysL2CacheLock)
        FUNC_EXPORT(_sysL2CacheUnlock)
#endif        
                
    _WRS_TEXT_SEG_START

/**************************************************************************
*	
* sysCachePpcLock -
*	
* This routine enables the cache , and load the cache with specified range
* of address and locks.
*
*/                
                    
FUNC_BEGIN(_sysL1CacheLock)
SYSL1CACHELOCK_STARTADRS: 
        mflr   r27
        mr     r28, r3
        mr     r29, r4
        mr     r30, r5

        cmpwi  r28, _DATA_CACHE
        beq    EnDataCache
        cmpwi  r28, _INSTRUCTION_CACHE
        beq    EnInstCache

EnDataCache:
        mfspr  r3, HID0
#if   (CPU == PPC603)        
        ori    r3, r3, _PPC_HID0_DCE
#elif (CPU == PPC604)
        ori    r3, r3, _PPC_HID0_DCE | _PPC_HID0_DCFI
#endif                
        sync
        mtspr  HID0, r3
        sync

LdNLkPpcDataCache:
        add    r30, r29, r30
loadD: 
        lwz    r20, 0(r29)
        addi   r29, r29, 32
        cmplw  r29, r30
        bge    lockD
        b      loadD

lockD:
        mfspr  r3, HID0
        ori    r3, r3, _PPC_HID0_DLOCK
        sync
        mtspr  HID0, r3
        sync
        b      RETLK

EnInstCache:    
        mfspr  r3, HID0
#if   (CPU == PPC603)        
        ori    r3, r3, _PPC_HID0_ICE
#elif (CPU == PPC604)
        ori    r3, r3, _PPC_HID0_ICE | _PPC_HID0_ICFI
#endif                
        isync
        mtspr  HID0, r3
        sync
       
LdNLkPpcInstCache: 
        add    r30, r29, r30
        lis    r3,  0x0000
        ori    r3, r3, 0x0001
        mtlr   r29

loadI:  divw.  r3, r3, r3
        beqlr+

        addi   r29, r29, 32
        mtlr   r29
        cmplw  r29, r30
        bge    lockI
        b      loadI

lockI:  
        mfspr  r3, HID0
        ori    r3, r3, _PPC_HID0_ILOCK
        isync
        mtspr  HID0, r3
        sync

RETLK:
        sync
        mtlr   r27
        blr
SYSL1CACHELOCK_ENDADRS:
FUNC_END(_sysL1CacheLock)
        
        
/**************************************************************************
*	
* _sysL1CacheUnlock -
*
* This routine unlocks previously locked cache.
*
*/                
        
FUNC_BEGIN(_sysL1CacheUnlock)      
        cmpwi  r3, _INSTRUCTION_CACHE
        beq    UnLkPpcInstCache
        
UnLkPpcDataCache:  
        mfspr  r3, HID0
        lis    r4, 0xFFFF
        ori    r4, r4, 0xEFFF
        and    r3, r3, r4
        sync
        mtspr  HID0, r3
        sync
        b      RETUNLK                
                 
UnLkPpcInstCache:       
        mfspr  r3, HID0
        lis    r4, 0xFFFF
        ori    r4, r4, 0xDFFF
        and    r3, r3, r4
        isync
        mtspr  HID0, r3
        isync
        
RETUNLK:
        blr                
FUNC_END(_sysL1CacheUnlock)      


/*#if defined(INCLUDE_CACHE_L2)*/
#ifdef INCLUDE_CACHE_L2
        
/************************************************************************
*
* _sysL2CacheLock - locks L2 cache with data or instruction.
*
* This routine locks L2 cache with data or instruction.
*
*/

FUNC_BEGIN(_sysL2CacheLock)
        mflr   r26
        mr     r27, r3
        mr     r28, r4
        mr     r29, r5

        add    r29, r28, r29
          
CACHE_TYPE:                            
        cmpwi  r27, _DATA_CACHE
        beq    LoadData
        cmpwi  r27, _INSTRUCTION_CACHE
        beq    LoadInst
        
LoadData:       
        lwz    r20, 0(r28)
        addi   r28, r28, 32
        cmplw  r28, r29
        bge    lockL2
        b      LoadData
                  

LoadInst:       
        lis    r3,  0x0000
        ori    r3, r3, 0x0001
        mtlr   r28

loadL2I:  divw.  r3, r3, r3
        beqlr+

        addi   r28, r28, 32
        mtlr   r28
        cmplw  r28, r29
        bge    lockL2
        b      loadL2I
        
lockL2:
        mfspr  r4, L2CR_REG
        oris   r4, r4, L2DO
        ori    r4, r4, L2IO
        mtspr  L2CR_REG, r4
        
RETL2LK:        
        sync
        mtlr   r26
        blr        
FUNC_END(_sysL2CacheLock)



/*******************************************************************
*	
* _sysL2CacheUnlock
*
*
*/
	
FUNC_BEGIN(_sysL2CacheUnlock)
        mfspr   r3, L2CR_REG
#if  defined(USER_I_CACHE_ENABLE) && defined(USER_D_CACHE_ENABLE)
        lis     r4, 0xFFBF
        ori     r4, r4, 0XFBFF
        and     r3, r3, r4
        mtspr   L2CR_REG, r3
        sync
        b       RETL2UNLK              
#elif defined(USER_I_CACHE_ENABLE)
        lis     r4, 0xFFBF
        ori     r4, r4, 0XFFFF
        and     r3, r3, r4
        mtspr   L2CR_REG, r3
        sync
        b       RETL2UNLK              
#elif defined(USER_D_CACHE_ENABLE)
        lis     r4, 0xFFFF
        ori     r4, r4, 0XFBFF
        and     r3, r3, r4
        mtspr   L2CR_REG, r3
        sync
        b       RETL2UNLK             
#endif
RETL2UNLK:
        blr                       
FUNC_END(_sysL2CacheUnlock)
#endif