config.h

PowerPC 74XX系列CPU的VxWorks BSP源代码！

/* config.h - sandpoint sp8240/755/7400 configuration header file */

/* Copyright 1984-2000 Wind River Systems, Inc. */

/*
modification history
--------------------
01z,18jul02,pcs  define SP8240 if either SP8241 or SP8245 is defined. Missed
                 it in the previous checkin.
01y,16jul02,pcs  define SP8240 if either SP8245 or SP8241 is defined.
01x,17may02,pcs  undef SNOOP_ENABLE , Add macros for WINDML support
01w,01may02,jnz  enable on chip duarts for 8245/8241 by default.
01v,01apr02,jnz  added support for 8245/8241 on chip duarts.
01u,07mar02,pcs  Add support for 7455.
01t,31jan02,pcs  Cleanup .
01s,24jan02,mil  Changed define of CPU7410 to SP7410 and define SP7400 if
                 SP7410 is defined.
01r,24jan02,pcs  Disable L2 cache if -DSP745 specified.
01q,22jan02,pcs  Merge the 7450 from T2.1
01p,21jan02,pcs  Cleanup: sync with sp74xx/config.h
01o,10jan02,pcs  Update DEFAULT_BOOT_LINE to reflect for 7450.
01n,10jan02,pcs  Bump up BSP_REV to 5 for the PPMC7450 support (sp745x BSP).
01m,03jan02,pcs  Add support for L2/L3 Cache (7450)
01l,31oct01,pcs  Add support for 7450.
01k,23may01,kab  Exclude ATA by default
01j,15may01,pch  Rename local floppy driver to fix clash with generic in
                 project facility 
01i,13apr01,mil  Added new -DCPU7410
01h,12apr01,mil  debug
01g,21mar01,pcs  DEBUGGING
01f,22jan01,pcs  Add support for sp750 as received from teamF1
01e,15jan01,pcs  Modify to make a non-altivec release.
01d,03dec00,ksn  BSP_REV set to 3, and added altivec, cache locking and
                 cache snooping support (teamF1)
01c,28sep00,ksn  changed bsp rev to 2 (teamF1)
01b,12sep00,ksn  added support for SP755 & SP7400 (teamF1)
01a,10oct99,mtl  written from SPS/Motorola & yk750 by teamF1.
*/

/*
This file contains the configuration parameters for the sandpoint BSP.
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
extern "C" {
#endif

/* BSP version/revision identification, before configAll.h */

#define BSP_VER_1_1     1
#define BSP_VERSION     "1.2"
#define BSP_REV         "/6"    /* 0 for first revision */

#include "configAll.h"          /* Set the VxWorks default configuration */

/* The MPC7410 shares the MPC7400 features in the scope of this BSP */

#ifdef SP7410
#  undef  SP7400
#  define SP7400                /* define both SP7410 and SP7400 */
#endif  /* SP7410 */

#if (defined(SP750) || defined(SP755)  || defined(SP745) )
#define DEFAULT_BOOT_LINE \
"dc(0,0)host:/target/config/sp7xx/vxWorks h=90.0.0.3 e=90.0.0.50 u=vxworks"
#elif  defined (SP7400)
#define DEFAULT_BOOT_LINE \
"dc(0,0)host:/target/config/sp74xx/vxWorks h=90.0.0.3 e=90.0.0.50 u=vxworks"
#elif  (defined (SP7450) || defined (SP7455) || defined (SP7441) || defined (SP7445)) 
#define DEFAULT_BOOT_LINE \
"dc(0,0)host:/target/config/sp745x/vxWorks h=90.0.0.3 e=90.0.0.50 u=vxworks"
#elif  (defined (SP8240) || defined (SP8245) || defined (SP8241))
#define DEFAULT_BOOT_LINE \
"dc(0,0)host:/target/config/sp824x/vxWorks h=90.0.0.3 e=90.0.0.50 u=vxworks"
#endif

/* User include/exclude section */

#define INCLUDE_SYSCLK			/* PPC decrementer system clock */
#define INCLUDE_AUXCLK			/* i8254 Aux clock driver 	*/
#define INCLUDE_SERIAL			/* i8250Sio.c serial driver 	*/
#define INCLUDE_NVRAM			/* NVRAM driver byteNvRam.c 	*/
#define INCLUDE_FLASH           	/* 29F040 flashDrv.c 		*/
#define INCLUDE_SYS_UPDATE_FLASH       	/* sysUpdateFlash() - sysLib.c 	*/ 
#define INCLUDE_MMU_BASIC		/* basic MMU support 		*/
#define INCLUDE_CACHE_SUPPORT   	/* cacheLib support 		*/
#define	INCLUDE_NETWORK			/* network code 		*/
#define	INCLUDE_NET_INIT		/* network startup code		*/
#define INCLUDE_PCI			/* pciConfigLib/pciIntLib 	*/
#define INCLUDE_FDC			/* PS2 floppy disk driver       */
#undef  INCLUDE_TIMESTAMP		/* PPC decrementer as timestamp */
#undef  INCLUDE_INSTRUMENTATION		/* windview optional product 	*/
#define	INCLUDE_CACHE_L2                /* include L2 cache support     */
#define INCLUDE_L2PM                    /* include L2 pvt mem support   */
#define	INCLUDE_CACHE_L3                /* include L3 cache support     */
#define INCLUDE_PRIMARY_END             /* Primary present              */
#undef	INCLUDE_USER_APPL               /* Include user application     */
#undef SNOOP_ENABLE                    /* enable snooping */
/* INCLUDES required for running VTS */

/* Note: This is a temp solution untill we are able to differentiate between 
 *        the MPC7450 & MPC7441 
 *        and MPC7455 & MPC7445
 *        based on some board specific information.
 */

#if defined(SP7441)
#define SP7450 
#undef INCLUDE_CACHE_L3
#endif

#if defined(SP7445)
#define SP7455
#undef INCLUDE_CACHE_L3
#endif

#if (defined(SP8241) || defined(SP8245))
#define SP8240
#endif

/* Note: The L2 Cache was not behaving consistently on the board on which
 *       this bsp was tested. So undef INCLUDE_CACHE_L2 for the present 
 *       untill the problem is resolved.  
 */
#if (defined(SP7445))
#undef INCLUDE_CACHE_L2
#endif

#if (defined(SP7400) || defined(SP7450) || defined(SP7455))
#define INCLUDE_ALTIVEC
#endif
#ifdef INCLUDE_ALTIVEC
#define INCLUDE_TASK_HOOKS              /* taskHookLib support */
#endif /* INCLUDE_ALTIVEC */

/*  NOTE:  The L3 cache is present only on the MPC7450. 
           So the define INCLUDE_CACHE_L3 is only revelant for the 
           sp745x BSP (Sandpoint Valis ). 
*/

#if !((defined(SP7450)) || (defined(SP7455)))
#undef  INCLUDE_CACHE_L3                /* include L3 cache support     */
#endif /* SP7450 */

#undef INCLUDE_DUART                    /* exclude duart by default */
#if defined(SP8245) || defined(SP8241)
#ifndef INCLUDE_DUART
#       define INCLUDE_DUART            /* include on chip duart support */
#endif /* INCLUDE_DUART */
#endif

/* memory configuration */

#define LOCAL_MEM_LOCAL_ADRS    0x0
#define LOCAL_MEM_SIZE          0x01000000      /* 16 M */

#define USER_RESERVED_MEM       0x0

#undef  LOCAL_MEM_AUTOSIZE                      /* run-time memory sizing */

/* 
 * Sandpoint/PPMC8240 SDRAM & MPC107 static memory bank configuration.
 *
 * The PPMC8240 has one DIMM slot. The DIMM module uses two memory banks.
 * There are eight memory banks on the MPC107 memory controller.  
 *
 * By default, the BSP is configured to support a single 8MB SDRAM DIMM
 * module residing in the PPMC DIMM slot.  16MB bank size is set for each bank
 * except Bank zero. Bank zero is enabled, bank one through seven disabled.
 *
 * The macro MPC107_BANK[x]_SIZE determines the size of the memory bank. 
 * The tested bank size is 8MB.  Other sizes are untested.
 * The default is 16MB for each bank except bank zero, whic is 8MB.
 * To change the default size for a particular bank, redefine the
 * macro for that bank.
 *
 * The macro MPC107_MBER_VAL defines which banks are enabled by the MPC107's
 * memory bank enable register.  The default is to enable bank 0,
 * which enables both memory banks on the DIMM in the slot.
 * 
 * Any change requires a rebuild of the bootrom image, and reprogramming
 * of the physical bootrom with the rebuilt image (bootrom.hex, etc.)
 * One must also define LOCAL_MEM_SIZE and USER_RESERVED_MEM accordingly.
 */

/* memory bank sizes. 8240 PMC uses 1. */

#define MPC107_BANK0_SIZE	BANKSIZE_SIXTEEN_MEG
#define MPC107_BANK1_SIZE	BANKSIZE_SIXTEEN_MEG
#define MPC107_BANK2_SIZE	BANKSIZE_SIXTEEN_MEG
#define MPC107_BANK3_SIZE	BANKSIZE_SIXTEEN_MEG
#define MPC107_BANK4_SIZE	BANKSIZE_SIXTEEN_MEG	
#define MPC107_BANK5_SIZE	BANKSIZE_SIXTEEN_MEG
#define MPC107_BANK6_SIZE	BANKSIZE_SIXTEEN_MEG
#define MPC107_BANK7_SIZE	BANKSIZE_SIXTEEN_MEG

/* bank sizes */

#define BANKSIZE_TWO_MEG	0x00200000	/*  2MB - 1/2  4MB DIMM */
#define BANKSIZE_FOUR_MEG	0x00400000	/*  4MB - 1/2  8MB DIMM */
#define BANKSIZE_EIGHT_MEG	0x00800000	/*  8MB - 1/2 16MB DIMM */
#define BANKSIZE_SIXTEEN_MEG	0x01000000	/* 16MB - 1/2 32MB DIMM */
#define BANKSIZE_THIRTYTWO_MEG	0x02000000	/* 32MB - 1/2 64MB DIMM */

/* setup which memory banks to enable */

#define MPC107_MBER_VAL         (MPC107_BANK0_ENABLE)

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
 * are defined in config.h and Makefile.
 * All definitions for these constants must be identical.
 */

#define ROM_BASE_ADRS           0xfff00000      /* base address of ROM */
#define ROM_TEXT_ADRS           (ROM_BASE_ADRS+0x0100) /* with PC & SP */
#define ROM_WARM_ADRS           (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */
#define ROM_SIZE                0x00080000      /* 512KB ROM space */
#define RAM_LOW_ADRS            0x00010000   /* RAM address for vxWorks */
#define RAM_HIGH_ADRS           0x00400000   /* RAM address for bootrom */


/* Serial port configuration */

#ifdef INCLUDE_DUART
#   define NUM_DUART_TTY    2
#else
#   define NUM_DUART_TTY    0
#endif /* INCLUDE_DUART */

#undef  NUM_TTY
#define NUM_TTY        N_SIO_CHANNELS+NUM_DUART_TTY  /* sio channel defined in sp.h */

#undef  WDB_COMM_TYPE 
#define WDB_COMM_TYPE  WDB_COMM_SERIAL /* communication through serial port */

#undef  WDB_TTY_BAUD
#define WDB_TTY_BAUD    38400

/*
 * Cache configuration
 *
 * Note that when MMU is enabled, cache modes are controlled by
 * the MMU table entries in sysPhysMemDesc[], not the cache mode
 * macros defined here.
 */

/* instruction cache */

#define	USER_I_CACHE_ENABLE		/* Enable INSTRUCTION CACHE */
#undef	USER_I_CACHE_MODE
#define USER_I_CACHE_MODE CACHE_COPYBACK /* select COPYBACK or WRITETHROUGH */