syscachelocklib.c

PowerPC 74XX系列CPU的VxWorks BSP源代码！

/* sysCacheLockLib.c - Cache locking support routines. */

/* Copyright 2000 Wind River, Inc */

/*
modification history
--------------------
01d,31jan02,pcs  Remove Diab compiler warnings.
01c,24jan02,mil  Added inclusion of config.h to define SP7400 ifdef SP7410.
01b,15Dec00,ksn  added support for L2 cache locking.
01a,12Dec00,mno  created (teamf1)

*/


/*
DESCRIPTION

This module contains code to lock and unlock L1 and L2 cache. The routines
sysCacheLock/Unlock can be used to lock and unlock the L1 cache while the
routines sysL2CacheLock/Unlock can be used to lock and unlock the L2 cache.

This module supports PPC processors that support separate data and instruction
caches (harward-style) for the L1. The lock routine will lock the entire
cache, after loading it with specified code or data region. When the cache is
locked, data/instruction access to regions not locked in the cache will not
hit the cache.

L1 locking routines can be used to lock only one region of memory. Multiple
calls to lock a region will result in unlocking the previous regionn. The
region being locked must be aligned on a 32-byte boundary, and must not be
larger than the L1 cache size.

L2 cache locking is currently supported only for 74X0 and 755 CPUs. These CPU
implement a unified L2 cache that cannot be locked for separately for data and
instruction. The implementation therefore supports locking the entire L2 cache
for either data or instruction. While locking the L2 cache, the corresponding
L1 cache must have been enabled, but not locked. Multiple calls to the L2
cache locking will silently unlock the region previously locked.

Just as the L1 cache, the region being locked in the L2 cache must be aligned
on a 32-byte boundary.

SEE ALSO: 
*/



/* includes */

#include "vxWorks.h"
#include "config.h"
#include "cacheLib.h"
#include "intLib.h"
#include "string.h"
#include "vmLib.h"
#include "private/vmLibP.h"
#include "arch/ppc/mmuPpcLib.h"
#include "tickLib.h"
#include "sysCacheLockLib.h"
#include "sysL2BackCache.h"


/* externs */

IMPORT STATUS cachePpcDisable(CACHE_TYPE cache);

/* defines */

#define CACHE_LOCK_AND_ENABLE_RTN_SIZE  ((int)SYSL1CACHELOCK_ENDADRS - \
                                         (int)SYSL1CACHELOCK_STARTADRS)

/***********************************************************************
*
* sysCacheLock - locks specified data/instruction region
*
* This routine locks the specified region into the cache, <cacheType>. The
* region to be locked is specified by the start address, <adrs>, and the size,
* <bytes>. The region -- the start address, and size -- must be aligned on a
* 32-byte boundary.
*
* Multiple calls to this routine will silently unlock the specified cache to
* lock the new region.
*
* RETURN - OK or error if cache is locked, or if cache is not supported.
*/

STATUS sysCacheLock
    (
    CACHE_TYPE cacheType,
    void * adrs,
    UINT32 bytes
    )
    {
    int x;
    VOIDFUNCPTR cacheEnableAndLockRtn;
    UINT32 cacheEnableAndLockRtnSize;

    if (!ALIGNED(adrs, 32))
        {
        logMsg("\n Memory Address not aligned on 32 byte boundry\n",1,2,3,4,5,6);
        return (ERROR);
        }
        
    if ((cacheType != _INSTRUCTION_CACHE) &&
        (cacheType != _DATA_CACHE))
        return (ERROR);
    
    x=intLock();

    /* if l1 is locked, unlock it */
    if ((vxHid0Get() & _PPC_HID0_DLOCK) || (vxHid0Get() & _PPC_HID0_ILOCK))
        sysCacheUnlock(cacheType);

    cachePpcDisable(cacheType);
    if (cacheType == _DATA_CACHE)
        cacheEnableAndLockRtn = _sysL1CacheLock;
    else
        {
        cacheEnableAndLockRtnSize =
            ROUND_UP(CACHE_LOCK_AND_ENABLE_RTN_SIZE, MMU_PPC_PAGE_SIZE);
        
        cacheEnableAndLockRtn = (VOIDFUNCPTR)
            cacheDmaMalloc (cacheEnableAndLockRtnSize);

        if (cacheEnableAndLockRtn == NULL)
            {
            intUnlock (x);
            return (ERROR);
            }
        
        VM_STATE_SET (NULL, (char *) cacheEnableAndLockRtn,
                      cacheEnableAndLockRtnSize,
                      VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
                      VM_STATE_CACHEABLE_NOT  | VM_STATE_MEM_COHERENCY_NOT);
        
        bcopy ((char*)SYSL1CACHELOCK_STARTADRS,
               (char *)cacheEnableAndLockRtn,
               CACHE_LOCK_AND_ENABLE_RTN_SIZE);
        }

    cacheEnableAndLockRtn (cacheType, adrs, bytes);
    intUnlock(x);
    
    if (cacheType == _INSTRUCTION_CACHE)
        cacheDmaFree ((char *)cacheEnableAndLockRtn);

    return (OK);
    }

/****************************************************************************
*
* sysCacheUnlock - Unlocks the previous locked cache
*
* This routines unlocks the specified cache, <cacheType>
*
* RETURN - OK or error if cache is not supported.
*/

STATUS sysCacheUnlock
    (
    CACHE_TYPE cacheType
    )
    {
    int x;

    if ((cacheType != _INSTRUCTION_CACHE) &&
        (cacheType != _DATA_CACHE))
        return (ERROR);

    if (cacheType == _DATA_CACHE)
        {
#if defined(INCLUDE_CACHE_L2)

#if defined(SP7400)
        sysL2BackHWFlush();        
#endif

#if defined(SP755)
        sysL2BackSWFlush();        
#endif
#endif
        }
        
    x = intLock();
    _sysL1CacheUnlock (cacheType);
    intUnlock(x);

    return (OK);
    }

#if defined(INCLUDE_CACHE_L2)

/*************************************************************************
*
* sysL2CacheLock - lock L2 cache
*
* The routine locks the L2 cache with specified region. L2 is implemented
* as a unified cache and supports locking only one region regardless of
* whether it is data or instruction.
*
* A region of data or instruction can be locked in L2 cache only when the
* corresponding L1 cache is enabled but not locked.
*
* The region of memory being locked must be aligned on a 32-byte boundary.
*
* On consequtive calls, this routine will silently unlock the previous locked
* region.
*
* RETURNS: OK on success, and ERROR otherwise.
*
* SEE ALSO: sysL2CacheUnlock, sysCacheLock, sysCacheUnlock
*
*/

STATUS sysL2CacheLock
    (
    CACHE_TYPE cacheType,
    void * adrs,
    size_t bytes
    )
    {
    UINT32  hid0;
    size_t  size;
    
    if ((cacheType != _INSTRUCTION_CACHE) &&
        (cacheType != _DATA_CACHE))
        return (ERROR);

    if (!ALIGNED(adrs, 32) ||
        !ALIGNED(bytes, 32))
        {
        logMsg("Memory Address and size are not aligned on 32 byte boundry\n",
               1,2,3,4,5,6);
        return (ERROR);
        }
        
    if (bytes > L2RAM_SIZE)
        size = L2RAM_SIZE;
    else
        size = bytes;
    
    hid0 = sysHID0Read();

    /*
     * For data cache lock, verify that L1 data cache is enabled
     * and that L1 data cache is not locked
     */

    if ((cacheType == _DATA_CACHE) &&
        ( !(hid0 & _PPC_HID0_DCE) ||
          (hid0 & _PPC_HID0_DLOCK)))
        return (ERROR);

    /*
     * For instruction cache lock, verify that L1 instruction cache is enabled
     * and that the instruction L1 cache is not locked
     */

    if ((cacheType == _INSTRUCTION_CACHE) &&
        (( ! (hid0 & _PPC_HID0_ICE)) ||
         (    hid0 & _PPC_HID0_ILOCK)))
        return (ERROR);
    
    /*  if l2 locked, unlock it*/
    if (sysL2CRRead() &  ((L2DO << 16) || L2IO))
        sysL2CacheUnlock();
    
    _sysL2CacheLock(cacheType, adrs, size);

    return (OK);
    }


/*************************************************************************
*
* sysL2CacheUnlock - unlock the L2 cache
*
* This routine unlocks the L2 cache.
*
* RETURNS: OK, always.
*
* SEE ALSO: sysL2CacheLock, sysCacheLock, sysCacheUnlock
*/

STATUS sysL2CacheUnlock (void)
    {
    _sysL2CacheUnlock();
    return (OK);    
    }    
#endif