target.nr

PowerPC 74XX系列CPU的VxWorks BSP源代码！

   | Top of RAM	       |  RAM_HIGH_ADRS		       0x0040 0000 |
   | containing	vxWorks|                                           |
   | (VxWorks code is  |                                           |
   | copied here from  |                                           |
   | ROM)	       |  RAM_LOW_ADRS		       0x0001 0000 |
   |___________________|__________________________________________ |
   |		       |                                           |
   |		       |                                           |  
   | Zeroed out	       |                                           |
   | by	boot code      |                                           |
   |		       |  Start	Of Interrupt Vectors   0x0000 0100 |
   |		       |  Physical Start Of RAM	       0x0000 0000 |
   |_______________________________________________________________|
.bE



.SS "Shared Memory"

The Sandpoint does not currently support a shared memory driver.

.SS "Interrupts"

The SandPoint BSP uses the MPC107 for PPMC750, PPMC755, PPMC7400 & PPMC7410
PPMC7450, PPMC7455, PPMC7441 & PPMC7445 and EPIC interrupt controller 
integrated in the MPC8240
micro-controller. Interrupt lines of PCI devices are connected to the
EPIC module or the MPC107, while the interrupt lines of the serial
port communications (COM1, COM2, AuxClock, Floppy, IDE) are connected
to the Winbond chip.

Interrupt functions that initialize and support the interupt
controller module are contained in the sysEpic.c and sysEpic.h
files. Interrupt functions that initialize and support the serial
communication are contained in the w83553PciIbc.c and w83553PciIbc.h
files.

Internally, the Winbond IRQs are numbered from 0x10 to 0x20, while the
EPIC/MPC107 IRQs are numbered from 0x0 to 0x4 (0x4 is not brought out
on the PPMC). The EPIC interrupt priorities are assigned according to
IRQ numbers.

COM1 is configured for IRQ4 and COM2 is configured for IRQ3 on the
Winbond device.  The winbond device is connected to IRQ2 of the EPIC
module.

The two serial communication channels are defined in sp.h. The serial
communications inclusion is determined by the macros INCLUDE_SERIAL
and NUM_TTY in config.h. The supported baud rates depend on the
i8250Sio.c driver. The BSP has been verified with the following baud
rates:

     115200, 57600, 38400, 19200, and 9600 baud.

.SS "SandPoint Board  Interrupt Architecture"
                        
.bS

                                                                                    
 ______________________________________________________________________________________
|                                                                                      |
|                                                                                      |
|                                                                                      |
|                               ____________________                                   |                    
|                              |                    |                                  |
|                              |   POWER PMC CARD   |                                  |                    
|                              |   ______________   |                                  |                
|                              |  |  EPIC/MPC107 |  |                                  |           
|                              |  |______________|  |                                  |        
|                              |         |          |                                  |
|                              |         |          |                                  |    
|                              |_________|__________|                                  |                       
|                               IRQ 0 to | IRQ 3            PCI-SLOTS                  |
|                                        |                       |  |                  |
|                                        |                       |  |                  |
|                                        |                 |  |  |  |                  |
|                                        |                 |  |  |  |                  |
|                                        |=================|==|==|==|                  |                            
|                                        |                 |  |  |  |                  |
|                                        |                 |  |  |  |                  |
|                                        |                                             |
|                                        |                                             |
|                                        |                                             |    
|                                        |                                             |  
|                               _________|__________                                   |
|                              |    Winbond 83553   |                                  |
|                              |   PCI/ISA  Bridge  |                                  |
|                              |____________________|                                  |
|                                        |                                             |
|                              IRQ 16 to |IRQ 31                                       |            
|                                        |                                             | 
|                                        |                                             |                  
|                                        |  ON-BOARD I/O                               |
|                                        |_______________                              |      
|                                                       |                              |                                                         
|                                                       |                              | 
|                                                       |                              |
|                                         ______________|______________                |
|                                        |        |          |         |               |                      
|                                        |        |          |         |               |              
|                                     COM-1    COM-2      FLOPPY      IDE              |                
|                                                                                      |                 
|                                                                                      | 
|                                                                                      |              
|                                                                                      |                
|                                                                                      |                 
|                                                                                      |               
|                                                                                      |           
|______________________________________________________________________________________|
 


.bE

EPIC Interrupt Table

.TS E
expand,tab(|);
lf3 lf3 lf3 
l l l.
IRQ | Priority | Description 
=
0 | 0 | PCI Slot 1     
1 | 1 | PCI Slot 2, shared with Winbond IRQ
2 | 2 | PCI Slot 3
3 | 3 | PCI Slot 4
4 | 4 | unused
.TE


Secondary  Interrupt Controller Winbond IRQ Table

.TS E
expand,tab(|);
lf3 lf3 lf3 
l l l.
IRQ | Priority | Description 
-

16 | 2 | i8254 Timer
17 | 2 | unused
18 | 2 | cascade
19 | 2 | COM2 / ttyb / tyCo 1
20 | 2 | COM1 / ttya / tyCo 0
21 | 2 | unused
22 | 2 | unused 
23 | 2 | unused
24 | 2 | unused
25 | 2 | unused
26 | 2 | unused
27 | 2 | unused
28 | 2 | unused
29 | 2 | unused
30 | 2 | IDE controller 0
31 | 2 | IDE controller 1
.TE

The sysLib.c routine sysIntConnect() will call the appropriate
intConnect routines, pciIntConnect() for PCI INTs, and intConnect() for
all others. See also, sysEpic.[ch], w83553PciIbc.[ch].

.SS "Serial Configuration"

The default kernel configuration, as delivered, includes two serial
communication ports com1 and com2, the Wind debugger WDB,
and one "dc" (DEC 2114x) ethernet port.

Com1: is used for terminal display. The VxWorks banner, all VxWorks
error messages, and all output generated by printfs in applications
programs are displayed on this terminal. Either a vt100 type dumb
terminal can be connected via a standard serial cable, or a vt100 type
terminal emulator program on a PC can be connected via a null modem
type serial cable.

Com2: is used for the WDB communication port. A null modem serial
cable can be connected to the com2 port of a PC or UNIX machine. The
Tornado program uses host shells to communicate to VxWorks on the
target.

Com1 and com2 are interrupt driven drivers using the code in
sysSerial.c. Com1 is configured for IRQ4 and com2 is configured for
IRQ3. The two serial communication channels are defined in sp.h as
COM1_ADR, COM1_INT_LEV, COM1_INT_VEC and corresponding com2
macros. sysLib.c calls the serial driver initialization functions
during sysHwInit calling sysSerialHwInit() and sysHwInit2() and
sysSerialHwInit2().  The serial communications inclusion is determined
by the macros INCLUDE_SERIAL and NUM_TTY in config.h.

.SS "SCSI Configuration"

This BSP does not support any SCSI devices at this time.

.SS "Network Configuration"

Ethernet communication is determined by the macro INCLUDE_NET in config.h.

Ethernet in the default version uses the DEC21140 ethernet chip set. It
is implemented by either the if_dc driver or an END driver. Other
cards supported are:

.CS 
        3COM 3C90x PCI 
        Intel fei82557 
        DEC 21143 chipset 
        AMD Ln97x 
.CE

.SS "VME Access"

No VME bus is present on the Sandpoint X2. 

.SS "PCI Access"

PCI access is controlled via the MPC107 PCI Bridge/Memory
Controller. Although this device supports three address mappings, the
SandPoint board supports only two.

Address map A conforms to the PowerPC reference platform specification (PReP).

Address map B conforms to the PowerPC microprocessor common hardware
reference platform (CHRP).

Some processor modules may have the address map (A or B) selection
hardwired on the module, and need to be ordered for Address Map B.
For details contact your Motorola sales office.
The 7400/7410 MPMC rev X3 module allows switch selection of the address
map via position 2 of SW2, which should be set to "off" to select
Address Map B.

Address map A or B selection is displayed upon booting with the
manufacturer-supplied DINK32 bootrom.

The function sysMemMapDetect() in sysLib.c detects the board
configuration for the memory maps. This function sets the system PCI
Configuration address and data address for Map B, MPC107_CFG_ADDR_CHRP
and MPC107_CFG_DATA_CHRP, into the appropriate variables, sysPciConfAddr
and sysPciConfData for the function sys107RegRead(). Then it calls
sys107RegRead which returns the value at that address. If the board
is configured for Address map B (CHRP), the value returned will be
the MPC107 vendor Id. If this is configured for Address map A (PREP),
then the value returned will be garbage, i.e. will not be the correct
Vendor Id. Thus, sysMemMapDetect() compares the returned value to the
Vendor Id, and if it is not true, then the Map A PCI Configuration
address and data addresses PREP_REG_ADDR and PREP_REG_DATA are placed
into the variables, sysPciConfAddr and sysPciConfData.

A similar algorithm is used in romInit.s during startup in the code
just prior to the function startMemInit(). This code only detects Map A
versus Map B for startup code, which is why it is necessary to do it
again in sysMemMapDetect() after VxWorks (or bootrom) gains control.

PCI Autoconfig is supported and is used to configure the resources for
each PCI device being used on the Sandpoint.

For more details, see MPC107 PCI Bridge/Memory Controller User's Manual.

.SS "Boot Devices"

Supported boot devices include:

.IP
fd=<ctrl>,<drive> - PS2 floppy device as boot device.
(if INCLUDE_FD is defined)
.CS
    \f3fd=<drive number>,<diskette type>\f1 - Diskette
        drive number is one of:
            0 = default; the first diskette drive (drive A:)
            1 = the second diskette drive (drive B:)
        diskette type is one of:
            0 = default; 3.5" diskette
            1 = 5.25" diskette
.CE

.IP
ata=<ctrl>,<drive> - EIDE/ATA HDD as boot device.
(if INCLUDE_ATA is defined)

.CS
    \f3ata=<controller number>,<drive number>\f1 - ATA/IDE drive
        controller number is one of:
            0 = primary controller described in the first entry 
                of the ataResources table
            1 = secondary controller described in the second entry 
                of the ataResources table
        drive number is one of:
            0 = first drive on the controller
            1 = second drive on the controller
.CE

Note: By default, with INCLUDE_ATA, vxWorks is set up for one ATA
hard disk device on the primary ATA controller. The 2nd hard disk on
the primary controller and the secondary controller are normally
disabled to prevent timeouts. If you have multiple controllers and/or
hard disks you must modify config.h ATA_DEV[x]_STATE values. See
config.h.
.LP

.IP
dc - DEC 21040/21140/21143 network device
(if PRIMARY_ENDTYPE == DEC_END_DEVICE in config.h for bootrom)
.IP
lnPci - AMD 79C970/79C971/79C972 network device
(if PRIMARY_ENDTYPE == AMD_END_DEVICE in config.h for bootrom)
.IP
fei - Intel 82557/82558/82559 network device
(if PRIMARY_ENDTYPE == FEI_END_DEVICE in config.h for bootrom)
.IP
elpci - 3Com 3c90X network device
(if PRIMARY_ENDTYPE == ELPCI_END_DEVICE in config.h for bootrom)
.IP
sl - SLIP network device
(if included in image)
.LP

.SS "Boot Methods"

The network support available for booting includes:
bootp, ftp, tftp, slip, and rsh.  


.SS "ROM Considerations"

The sysLib.c routine sysUpdateFlash() will rewrite the 29F040 flash
with data from a binary file <filename>.

This code allows the user to overwrite the flash device with data from
file <filename> using the low level flash support routines
sysFlashSet() and sysFlashGet() from src/drv/mem/flashMem.c. It writes
data to the flash device via sysFlashSet(), and verifies that the data
was written correctly. Writes to flash are wrapped within taskLock()
and intLock().  The user should pass a binary bootrom file; for
example to update the bootrom with a VxWorks BSP bootrom image:

.CS 
% make bootrom.bin

 -> sysUpdateFlash ("hostname:/tmp/bootrom.bin")
The flash has been updated without error.
->
.CE

.SS "ROM Programs" 

The ROM is a 29F040B, or equivalent, in position U6. Building any of
the following targets will create a Motorola S-record file suitable
for downloading to most ROM programmers: 

.IP 
bootrom.hex 
.IP
vxWorks.st_rom.hex 
.LP 

Note that the make will abort if the image will not fit in the 512K