📄 sysl2backcache.s
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ori r4, r4, LO(BUFFER_ADDR) subi r4,r4,(L1CACHE_ALIGN_SIZE) andi. r5, r5, 0x0 FlushCache: lbzu r5, L1CACHE_ALIGN_SIZE(r4) bdnz FlushCache sync blrFUNC_END(sysL2BackSWFlush) /********************************************************************** sysL2BackSetWT - Sets L2 Cache in writeThrough mode. ** The value of the l2cr register is read, the writethrough bit is * set and written back to the l2cr register.* * RETURNS: N/A** void sysL2SWFlush* (* void* )**/ FUNC_BEGIN(sysL2BackSetWT) isync sync mfspr r3, L2CR_REG oris r3, r3, L2CR_WT mtspr L2CR_REG, r3 sync blr /* return to caller */FUNC_END(sysL2BackSetWT) /********************************************************************** sysL2BackAutoSize - Autosize L2 Backside cache ** L2 backside cache is available on MPC75X and MPC 74X0 only. The* L2 cache size could be 1M, 512K, or 256K, or 2M on the 7410. The* size is programmed in the L2CR register.** To detect the correct size, this function assumes that the* L2 cache size is 2M, the cache is put in test mode so that a * cache flush operation (dcbf) will write from L1 cache to L2. 2M* of data is written to memory, then read back. If the cache size* is truely 2M, all data read back will be correct as expected. If* the cache size is 512 KB, half of the data will be correct, and * the other half is not, and so on. Once the size is determined,* the value that must be set in L2CR when the L2 backside cache is* enabled is stored in r3.* * There is no real way to distinguish MPC740 and MPC750; they both* have the same PRV number. After writing to L2 backside cache, if* the result is neither 1M, 512 KB, or 256 KB, it must be MPC740* (no L2 backside cache, r3 is set to 0).** RETURNS: the value of L2CR is returned in r3* ULONG sysL2BackAutoSize* (* void* )*/FUNC_BEGIN(sysL2BackAutoSize) andi. r3, r3, 0x0 andi. r0, r0, 0x0 andi. r5, r5, 0x0 /* Make r5 to be 0 */ andi. r30, r30, 0x0 /* Make r30 0 */ addis r4, r0, 0x0 /* Count index reg. */ addis r6, r0, WRITE_ADDR_U /* Address to start writing */ addis r5, r0, L2_SIZE_2M_U /* Memory chunk to write to */ l2SzWriteLoop: dcbz r4, r6 /* zero out the cache line */ stwx r4, r4, r6 /* write index to a cache line */ dcbf r4, r6 /* flush cache to L2 */ addi r4, r4, L2_ADR_INCR /* Increase the address index */ cmp 0, 0, r4, r5 blt l2SzWriteLoop addis r4, r0, 0x0 /* Count index reg. - reset to 0 */l2SzReadLoop: lwzx r7, r4, r6 /* Load a word from the cache line */ cmp 0, 0, r4, r7 /* Same as indexing value ? */ bne l2SkipCount addi r30, r30, 0x1 /* Count cache line read correctly */l2SkipCount: dcbi r4, r6 /* Invalidate the cache line */ addi r4, r4, L2_ADR_INCR /* increase the address index */ cmp 0, 0, r4, r5 /* Any memory space to read ? */ blt l2SzReadLoop addis r7, r0, L2CR_SIZE_2MB /* Load 2M l2cr value */ cmpi 0, 0, r30, L2_SIZE_2M /* 2M l2 backside cache ? */ beq l2AutoSizeDone addis r7, r0, L2CR_SIZE_1MB /* Load 1M l2cr value */ cmpi 0, 0, r30, L2_SIZE_1M /* 1M l2 backside cache ? */ beq l2AutoSizeDone addis r7, r0, L2CR_SIZE_512KB /* Load 512 KB l2cr value */ cmpi 0, 0, r30, L2_SIZE_HM beq l2AutoSizeDone addis r7, r0, L2CR_SIZE_256KB /* Load 256K l2cr reg. value */ cmpi 0, 0, r30, L2_SIZE_QM beq l2AutoSizeDone addis r7, r0, 0x0 /* No L2 cache */l2AutoSizeDone: addis r30, r0, 0x0 /* Save the value of l2cr in r30 */ addi r30, r7, 0x0 addi r3, r7, 0x0 blr FUNC_END(sysL2BackAutoSize)/*********************************************************************** sysPVRReadBoot - Read the content of the PVR register** Once the PVR is read, the 16 least significant bits are shifted off** RETURNS: the upper 16 bits of the PVR is returned in r3* ULONG sysPVRReadBoot* (* void* )*/FUNC_BEGIN(sysPVRReadBoot) mfspr r4, PVR_REG /* read PVR */ srawi r3, r4, 16 /* shift off the least 16 bits */ blrFUNC_END(sysPVRReadBoot) /*********************************************************************** sysL2CRWrite - Write a value to the L2CR register** RETURNS: N/A* void sysL2CRWrite* (* ulong value /@ value to write to the L2CR register is passed in r3 @/* )*/FUNC_BEGIN(sysL2CRWrite) sync mtspr L2CR_REG, r3 sync blrFUNC_END(sysL2CRWrite)/*********************************************************************** sysL2CRRead - Read a value from the L2CR register** RETURNS: the contents of L2CR register * ulong sysL2CRRead* (* void* )*/FUNC_BEGIN(sysL2CRRead) sync mfspr r3, L2CR_REG sync blrFUNC_END(sysL2CRRead)/*********************************************************************** sysHID0Write - Write a value to the HID0 register** RETURNS: N/A* void sysHID0Write* (* ulong value /@ value to write to the HID0 register is passed in r3 @/* )*/FUNC_BEGIN(sysHID0Write) sync mtspr HID0_REG , r3 sync blrFUNC_END(sysHID0Write)/*********************************************************************** sysHID0Read - Read a value from the HID0 register** RETURNS: the contents of HID0 register * ulong sysHID0Read* (* void* )*/FUNC_BEGIN(sysHID0Read) sync mfspr r3, HID0_REG sync blrFUNC_END(sysHID0Read) /********************************************************************** sysL2BackInit - Initialize L2 Back Cache.** RETURNS: N/A* void sysL2BackInit* (* void* )*/FUNC_BEGIN(sysL2BackInit) mfspr r9, PVR_REG /* read PVR */ rlwinm r9,r9,16,16,31 /* shift down 16 bits */ cmpli 0,0,r9,CPU_TYPE_7450 /* Vger pvr */ beq cache_init_L2_MPC745X cmpli 0,0,r9,CPU_TYPE_7455 /* 0x8001 */ beq cache_init_L2_MPC745X mfspr r3, L2CR_REG andis. r4, r3, L2CR_EN_U bne l2backenable_done mflr r7 sync addi r3, r0, 0x0 oris r3, r3, L2CR_CLK_2 mtspr L2CR_REG, r3 sync bl sysL2BackGlobalInv sync mfspr r3, L2CR_REG oris r3, r3, L2CR_CFG mtspr L2CR_REG, r3 sync isync mtlr r7l2backenable_done: blrcache_init_L2_MPC745X: mfspr r3, L2CR_REG andis. r4, r3, L2CR_EN_U bne l2backenable_done sync lis r5,0x8000 ori r5,r5,0x0000 lis r4,0x7011 ori r4,r4,0x1000 and r3,r3,r4 mtspr L2CR_REG,r3 sync mflr r7 bl sysL2BackGlobalInv isync mtlr r7 blrFUNC_END(sysL2BackInit) /*********************************************************************** sysL1DcacheEnable - Enable the L1 Dcache** RETURNS: N/A* void sysL1DcacheEnable* (* void* )*/FUNC_BEGIN(sysL1DcacheEnable) mfspr r5,HID0_REG /* turn on the D cache. */ ori r5,r5,L1_DCACHE_ENABLE /* Data cache only! */ andi. r6,r5,L1_DCACHE_INV_MASK /* clear the invalidate bit */ mtspr HID0_REG,r5 isync sync mtspr HID0_REG,r6 isync sync blr FUNC_END(sysL1DcacheEnable)/*********************************************************************** sysL1DcacheDisable - Disable the L1 Dcache** RETURNS: N/A* void sysL1DcacheDisable* (* void* )*/FUNC_BEGIN(sysL1DcacheDisable) mfspr r5,HID0_REG andi. r5,r5,L1_DCACHE_DISABLE mtspr HID0_REG,r5 isync sync blr FUNC_END(sysL1DcacheDisable)#if defined(INCLUDE_L2PM) && (defined(SP755) || defined(SP7410))/*********************************************************************** sysL2PMEnable - Enable the Private Memory in L2 Cache Ram for MCP755 ** RETURNS: N/A* void sysL2PMEnable* (* void* )*/FUNC_BEGIN(sysL2PMEnable) isync sync addi r3, r0, 0x0 oris r3, r3, L2PMBA ori r3, r3, L2PM_SIZE mtspr L2PM_REG, r3 sync blrFUNC_END(sysL2PMEnable) #endif /* INCLUDE_L2PM && (SP755 || SP7410) */ ⌨️ 快捷键说明
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