sp.h

PowerPC 74XX系列CPU的VxWorks BSP源代码！

#ifndef PCI_CFG_FORCE
#    define PCI_CFG_FORCE		0x0     /* UNSUPPORTED */
#endif

#ifndef PCI_CFG_AUTO
#     define PCI_CFG_AUTO		0x1	/* IS SUPPORTED */
#endif
        
#ifndef PCI_CFG_NONE
#    define PCI_CFG_NONE		0x2	/* UNSUPPORTED */
#endif

/* PCI configuration type */

/* The Sandpoint must use pciAutoConfigLib.[ch] */

#define PCI_CFG_TYPE		PCI_CFG_AUTO 


/*
 * The following four macros define the default PCI XINT to EPIC IRQ 
 * level routing.  These are used in sysBusPci.c and sl82565IntrCtrl.c
 */

#define PCI_XINT1_LVL		0x0	/* PCI XINT1 routed to EPIC IRQ0  */
#define PCI_XINT2_LVL		0x1	/* PCI XINT2 routed to EPIC IRQ1 */
#define PCI_XINT3_LVL		0x2	/* PCI XINT3 routed to EPIC IRQ2 */
#define PCI_XINT4_LVL		0x3	/* PCI XINT4 routed to EPIC IRQ3 */

/* This is used as a offset from PCI slot 1 */

#define PCI_SLOT1_DEVNO		0xd	/* PCI SLOT 1 Device no */



/* PPC Decrementer - used as vxWorks system clock */

#define DELTA(a,b)     		(abs((int)a - (int)b))

/* This value MUST match the Sandpoint system 60x bus speed */

#ifndef DEC_CLOCK_FREQ
#define DEC_CLOCK_FREQ 		66666666	/* 66MHz default */
#endif


/* intel 8254 timer on the W83C553 - used as the vxWorks auxilary clock */

/* 
 * TIMER_HZ is the value input to the i8254 CLK pin.
 * On the W83C553, the i8254 CLK pin is internally routed from
 * the W83C553 cip OSC (pin#172) INPUT, which is divided down by 12.
 * On the Sandpoint, this OSC input is 14.31818 MHz as generated 
 * from the CDC9843 clock synth and FPX143 XTAL combination.
 * The macro TIMER_HZ below represents this configuration.
 */

#define TIMER_HZ		(14318180 / 12)
#define INT_LVL_TIMER0     (INT_NUM_IRQ0 + 0)
#define INT_VEC_TIMER0     (INT_VEC_IRQ0 + 0)
#define	MD_TERMCOUNT		0x0	/* interrupt on terminal count	*/
#define	MD_HWONESHOT		0x1	/* hw retriggerable one shot	*/
#define	MD_RATEGEN		0x2	/* rate generator		*/
#define	MD_SQUAREWV		0x3	/* square wave generator	*/
#define	MD_SWTRIGSB		0x4	/* software triggered strobe	*/
#define	MD_HWTRIGSB		0x5	/* hardware triggered strobe	*/

#define SL82565_TRM1_CNT0	0x0040
#define SL82565_TRM1_CNT1	0x0041
#define SL82565_TRM1_CNT2	0x0042
#define SL82565_TRM1_CMOD	0x0043

#define	CW_BCDMD		0x1	/* operate in BCD mode		*/
#define	CW_COUNTLCH		0x00	/* counter latch command	*/
#define	CW_LSBYTE		0x10	/* r/w least signif. byte only	*/
#define	CW_MSBYTE		0x20	/* r/w most signif. byte only	*/
#define	CW_BOTHBYTE		0x30	/* r/w 16 bits, lsb then msb	*/
#define	CW_READBK		0xc0	/* read-back command		*/
#define	CW_MODE(x)		((x)<<1)/* set mode to x		*/
#define	CW_SELECT(x)		((x)<<6)/* select counter x		*/

/* BSP timer constants */

#define SYS_CLK_RATE_MIN        3      /* minimum system clock rate */
#define SYS_CLK_RATE_MAX        5000   /* maximum system clock rate */

/* BSP min aux clock rate */

#define AUX_CLK_RATE_MIN        ((TIMER_HZ / 0xffff) + 1)  /* 8254 timer */
#define AUX_CLK_RATE_MAX        5000   /* maximum auxiliary clock rate */

/* static interrupt vectors/levels (configurable defs go in config.h) */

#define INT_VEC_IRQ0		0x10
#define INT_NUM_IRQ0            INT_VEC_IRQ0
#define EXT_INTERRUPT_BASE 	INT_NUM_IRQ0


/* NVRAM */

#if defined (INCLUDE_NVRAM)
#    define NV_RAM_SIZE		255
#    define NV_RAM_ADRS		00000000	/* this is an offset */
#    define NV_RAM_INTRVL	00000001
#    define NV_RAM_READ(x)	sysNvRead(x)	/* sysLib.c */
#    define NV_RAM_WRITE(x,y)	sysNvWrite(x,y)	/* sysLib.c */
#    define MSB_INDX_REG	0x74	
#    define LSB_INDX_REG	0x75
#    define DATA_REG		0x76
#    define NV_RAM_MSB_REG	(PCI_MSTR_ISA_IO_LOCAL + MSB_INDX_REG)
#    define NV_RAM_LSB_REG	(PCI_MSTR_ISA_IO_LOCAL + LSB_INDX_REG)
#    define NV_RAM_DAT_REG	(PCI_MSTR_ISA_IO_LOCAL + DATA_REG)
     /* NV_RAM_CSX_CNFG = 0x30 = A0-A3 enabled, CS on RW, A0-A11 decoded */
#    define NV_RAM_CSX_CNFG	0x30	
#else
#    define NV_RAM_SIZE		0
#    define NV_RAM_ADRS		00000000
#    define NV_RAM_INTRVL	00000000
#endif /* INCLUDE_NVRAM */

/* 29F040 flash support */

#   define FLASH_ADRS		0xff800000	/* Flash device on Bank 1 */
#   define FLASH_SIZE		0x00080000	/* 512 bytes */
#   define FLASH_WIDTH		1		/* 1 byte wide */
#   define FLASH_SIZE_WRITEABLE	FLASH_SIZE	/* write all of flash */
#   define SYS_FLASH_TYPE	FLASH_29F010	/* same algorythm as 29F040 */
#   define SYS_FLASH_WRITE			/* enable writting to flash */
#   define FLASH_NO_OVERLAY			/* blow away old flash data */
#   define SYS_FLASH_BOARD_DELAY		/* sysLib.c uSec delay rtn. */

#if CPU==PPC603
#   define WRONG_CPU_MSG "A PPC603 VxWorks image cannot run on a PPC604!\n";
#else
#   define WRONG_CPU_MSG "A PPC604 VxWorks image cannot run on a PPC603!\n";
#endif

#define CPU_TYPE        ((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_601    0X01    /* PPC 601 CPU */
#define CPU_TYPE_602    0x02    /* PPC 602 CPU */
#define CPU_TYPE_603    0x03    /* PPC 603 CPU */
#define CPU_TYPE_603E   0x06    /* PPC 603e CPU */
#define CPU_TYPE_603P   0x07    /* PPC 603p CPU */
#define CPU_TYPE_604    0x04    /* PPC 604 CPU */
#define CPU_TYPE_604E   0x09    /* PPC 604e CPU */
#define CPU_TYPE_604R   0x0A    /* PPC 604r CPU */
#define CPU_TYPE_750    0x08    /* PPC 750  CPU */
#define CPU_TYPE_8240   0x81    /* PPC 8240 CPU */
#define CPU_TYPE_8245   0x8081    /* PPC 8245 CPU */
#define CPU_TYPE_7400   0x0C    /* PPC 7400 CPU */
#define CPU_TYPE_7410   0x800C  /* PPC 7410 CPU */
#define CPU_TYPE_7450   0x8000  /* PPC 7450 CPU */
#define CPU_TYPE_7455   0x8001  /* PPC 7455 CPU */
#define CPU_TYPE_745    0x3202  /* PPC 745 CPU */
#define CPU_TYPE_755    0x3200  /* PPC 755 CPU */
#define CPU_VER_745   0x3100  /* Processor verion for MPC745/755 */
#define CPU_VER_750     0x0202  /* Processor version for MPC750 */
#define CPU_VER_740     0x0200  /* Processor version for MPC740 */
    
/* C PPC syncronization macro */

#define PPC_EIEIO_SYNC	WRS_ASM (" eieio; sync")	

/*
 * sysPhysMemDesc[] dummy entries:
 * these create space for updating sysPhysMemDesc table at a later stage
 * mainly to provide plug and play
 */

#define DUMMY_PHYS_ADDR         -1
#define DUMMY_VIRT_ADDR         -1
#define DUMMY_LENGTH            -1
#define DUMMY_INIT_STATE_MASK   -1
#define DUMMY_INIT_STATE        -1

#define DUMMY_MMU_ENTRY		{ 				\
				    (void *) DUMMY_PHYS_ADDR,	\
                                    (void *) DUMMY_VIRT_ADDR,	\
                                    DUMMY_LENGTH,		\
                                    DUMMY_INIT_STATE_MASK,	\
                                    DUMMY_INIT_STATE		\
                                }

/* create a single macro INCLUDE_MMU */

#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
#   define INCLUDE_MMU
#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */

/* 
 * Enforce some INCLUDE's which are not optional to the user.
 */

#ifdef INCLUDE_MMU_FULL			/* Full overrides basic */
#    undef INCLUDE_MMU_BASIC
#endif /* INCLUDE_MMU_FULL */

#ifdef INCLUDE_NETWORK			/* Network means PCI */
#    ifndef INCLUDE_PCI
#        define INCLUDE_PCI
#    endif
#endif /* INCLUDE_NETWORK */

#ifdef  INCLUDE_PCI			/* Sandpoint uses PCI autoconfig.*/
#    ifndef INCLUDE_PCI_AUTOCONF
#        define INCLUDE_PCI_AUTOCONF
#    endif
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_SYS_FLASH_UPDATE		/* sysFlashUpdate needs INCLUDE_FLASH */
#    ifndef INCLUDE_FLASH
#	define INCLUDE_FLASH
#    endif
#endif /* INCLUDE_SYS_FLASH_UPDATE */


/* END network configuration */

#if defined(INCLUDE_END) && defined(INCLUDE_NETWORK)

#define DEC_END_DEVICE		1		/* dc END */
#define FEI_END_DEVICE		2		/* fei END */
#define AMD_END_DEVICE		3		/* lnPci END */
#define ELPCI_END_DEVICE	4		/* elPci END */

#if (PRIMARY_ENDTYPE == DEC_END_DEVICE)
#ifndef INCLUDE_DC_END
#define INCLUDE_DC_END
#endif
#define SYS_END_LOAD_FUNC_PRI 	sysDec21x40EndLoad
#define SYS_END_BUFF_LOAN_PRI 	1
#endif

#if (PRIMARY_ENDTYPE == FEI_END_DEVICE) 
#ifndef INCLUDE_FEI_END
#define INCLUDE_FEI_END
#endif
#define SYS_END_LOAD_FUNC_PRI 	sysFei82557EndLoad
#define SYS_END_BUFF_LOAN_PRI 	1
#endif

#if (PRIMARY_ENDTYPE == AMD_END_DEVICE)
#ifndef INCLUDE_LN_97X_END
#define INCLUDE_LN_97X_END
#endif
#define SYS_END_LOAD_FUNC_PRI 	sysLn97xEndLoad
#define SYS_END_BUFF_LOAN_PRI 	1
#endif

#if (PRIMARY_ENDTYPE == ELPCI_END_DEVICE)
#ifndef INCLUDE_EL_3C90X_END
#define INCLUDE_EL_3C90X_END
#endif
#define SYS_END_LOAD_FUNC_PRI 	sysEl3c90xEndLoad
#define SYS_END_BUFF_LOAN_PRI 	1
#endif

#endif /* defined(INCLUDE_END) && defined (INCLUDE_NETWORK)*/

#ifdef DOC	/* For generating WRS documentation */
#ifndef INCLUDE_TIMESTAMP
#define INCLUDE_TIMESTAMP
#endif
#ifndef INCLUDE_SHOW_ROUTINES
#define INCLUDE_SHOW_ROUTINES
#endif
#define INCLUDE_FLASH
#define INCLUDE_SYSCLK			/* PPC decrementer system clock */
#define INCLUDE_AUXCLK			/* i8254 Aux clock driver 	*/
#define INCLUDE_SERIAL			/* i8250Sio.c serial driver 	*/
#define INCLUDE_NVRAM			/* NVRAM driver byteNvRam.c 	*/
#define INCLUDE_FLASH           	/* 29F040 flashDrv.c 		*/
#define INCLUDE_SYS_UPDATE_FLASH       	/* sysFlashUpdate() - sysLib.c 	*/ 
#define INCLUDE_MMU_BASIC		/* basic MMU support 		*/
#define INCLUDE_CACHE_SUPPORT   	/* cacheLib support 		*/
#define	INCLUDE_NETWORK			/* network code 		*/
#define	INCLUDE_NET_INIT		/* network startup 		*/
#define INCLUDE_PCI			/* pciConfigLib/pciIntLib 	*/
#define INCLUDE_ATA			/* ATA / EIDE HDD driver 	*/
#define INCLUDE_DC_NETIF
#define INCLUDE_DC_END
#define INCLUDE_FEI_END
#define INCLUDE_LN_97X_END
#define INCLUDE_EL_3C90X_END
#define INCLUDE_FDC
#endif /* DOC */

#undef  INCLUDE_SM_NET		/* No SM NET support */
#undef  INCLUDE_ENP		/* No ENP10  support */
#undef  INCLUDE_EX		/* No Exelan support */

/*
 * The board has a switch (S5) which allows the control of interrupt
 * polarity. It is set to inverted poloarity for now.
 */

#define EPIC_INT_POLARITY       0x0     /* Interrupt polarity */

#define WB_INT_POLARITY       	0x1     /* Interrupt polarity for Winbond */

#define WB_IRQ_WITH_SLOT3	2  	/* IRQ level of W83553 on EPIC */

#define WB_IRQ_WITH_SLOT2	1  	/* IRQ level of W83553 on EPIC */

#define WB_IRQ    		WB_IRQ_WITH_SLOT2
    
#ifdef __cplusplus
}
#endif

#endif	/* __INCsph */