rominit.s

VxWorks的bootloader实现

CPU_IS_603:
	/* 603, 603E, 603P jump here; 604R and unrecognized fall in */
	ori	r3, r3, (_PPC_HID0_ICE | _PPC_HID0_DCE)
	or	r4, r4, r3		/* set bits */
	sync
	isync
	mtspr   HID0, r4		/* HID0 = r4 */
	isync
	andc	r4, r4, r3		/* clear bits */
	cmpli   0, 0, r28, CPU_TYPE_604
	beq	CPU_IS_604
	cmpli   0, 0, r28, CPU_TYPE_604E
	beq	CPU_IS_604
        cmpli   0, 0, r28, CPU_TYPE_604R
        beq     CPU_IS_604
/* Following can't happen -- CPU_TYPE_750 is found earlier and never gets here
 *      cmpli   0, 0, r28, CPU_TYPE_750
 *      beq     CPU_IS_750
 */
	/* 603, 603E, 603P, unrecognized */
	isync
	mtspr	HID0, r4
	isync

#ifdef USER_I_CACHE_ENABLE
	b	I_CACHE_ON_603
#else
	b	MPC107_INIT
#endif

CPU_IS_7410:
	andi.	r3, r3, 0
	mtspr	1016, r3	/* 7410 bug, L2PMCR not cleared on reset */

CPU_IS_750:
	/* Handle 750, 7400, 7410 */
        mfspr   r3,HID0

        addis   r4,r0,0x0000    /* Clear r4 */
        ori     r4,r4,0x8800    /* Setup bit pattern for ICE/ICFI */
        or      r3,r4,r3
        isync
        mtspr   HID0,r3         /* set ICE/ICFI */
        isync

        addis   r4,r0,0x0000    /* Clear r4 */
        ori     r4,r4,0x0800    /* Setup bit pattern for ICFI */
        andc    r3,r3,r4
        isync
        mtspr   HID0,r3         /* clear IFCI (bit 16) */
        isync

        addis   r4,r0,0x0000    /* Clear r4 */
        ori     r4,r4,0x2000    /* Setup bit pattern for ILOCK */
        andc    r3,r3,r4
        isync
        mtspr   HID0,r3         /* clear ILOCK (bit 18) */
        isync
        sync
        b       MPC107_INIT
CPU_IS_7450:

	mfspr   r3, HID0
        sync
        oris    r3,r3,0x0400            # Set TBEN
        oris    r3,r3,0x0010            # Set DPM
        mtspr   HID0, r3
        sync
        b       CPU_IS_750

CPU_IS_604:
	/* 604, 604E, 604R, only */
	/* Enables and invalidates have been set in HID0,
	 * and the corresponding bits are cleared in r4.
	 * Loop count not increased for 7400, since it doesn't come here.
	 */
	LOADPTR (r5, 0x1000)		/* loop count, 0x1000 */
	mtspr	CTR, r5

LOOP_DELAY:
	nop
	bdnz	LOOP_DELAY
	isync
	mtspr 	HID0, r4
	isync

	/* turn the Instruction cache ON for faster FLASH ROM boots */

#ifdef USER_I_CACHE_ENABLE

        ori     r4, r4, (_PPC_HID0_ICE | _PPC_HID0_ICFI)
	isync				/* Synchronize for ICE enable */
        mtspr   HID0, r4                /* Enable Instr Cache & Inval cache */
	isync
	b    	MPC107_INIT

I_CACHE_ON_603:
	/* 603, 603E, 603P, unrecognized */
	ori	r4, r4, (_PPC_HID0_ICE | _PPC_HID0_ICFI)
        rlwinm  r3, r4, 0, 21, 19	/* clear the ICFI bit */

        /*
         * The setting of the instruction cache enable (ICE) bit must be
         * preceded by an isync instruction to prevent the cache from being
         * enabled or disabled while an instruction access is in progress.
         */
	isync
        mtspr   HID0, r4                /* Enable Instr Cache & Inval cache */
        mtspr   HID0, r3                /* using 2 consec instructions */
                                        /* PPC603 recommendation */
	isync
#endif

MPC107_INIT:
	/* All processor types end up here */
	/*
	 * Below we setup the MPC107 embedded memory controller.
	 * This procedure detects the MPC107's address map configuration.
         * Address map A conforms to the PowerPC reference platform
	 * specification (PReP). Map B conforms to the PowerPC
	 * microprocessor common hardware reference platform (CHRP).
	 * A board pull up/down resistor selects the map in hardware.
         * We assume that the memory map is Map B (Sandpoint default),
         * and attempt to read the MPC107's PCI Vendor and Device IDs.
         * If we read it ok, then use map B, else assume map A.
         * Emulation mode address mapping is not suppported.
	 * No "compatability hole" is configured.
	 */

	LOADPTR (r5, MPC107_CFG_ADDR_CHRP)
	LOADPTR (r6, MPC107_CFG_DATA_CHRP)
	addis   r9,r0, MPC107_PICR1_MAPB   /* r9 is used later to select map */

	LOADPTR (r4, MPC107_DEV_ID)
	addis   r3,r0, MPC107_CFG_BASE_16
	stwbrx  r3,0,r5
        sync                              /* NOTE: sync is needed here   */
                                          /*       to take care of 7450  */
                                          /*       load/store reordering */
        lwbrx   r3,r0,r6
	cmp     0,0,r3,r4
	beq     cr0, startMemInit	/* if we found ID, then init mem */
	LOADPTR (r4, PCI_DEV_ID_8240)
	cmp     0,0,r3,r4
	beq     cr0, startMemInit	/* if we found ID, then init mem */
	LOADPTR (r4, PPMC8245_ID)
	cmp     0,0,r3,r4
	beq     cr0, startMemInit	/* if we found ID, then init mem */

	LOADPTR (r5, MPC107_CFG_ADDR_PREP)/* else setup map A and init mem */
	LOADPTR (r6, MPC107_CFG_DATA_PREP)
	addis   r9,r0, MPC107_PICR1_MAPA  /* r9 is used later to select map */

startMemInit:

	/*
	 * we have proper map setting in r9, now setup the MPC107 for
	 * the Sandpoint board.
         */

	/*
	 * First setup the PCI cmd register and clear the PCI status reg
         *
         */

	LOADPTR (r3, MPC107_PCICMD_ADRS)  /* program MPC107's PCI cmd reg. */
	stwbrx	r3, 0,r5
    	LOADPTR (r4, MPC107_PCICMD_VAL)
    	sthbrx  r4, 0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_PCISTAT_ADRS) /* Program MPC107's PCI status reg. */
	stwbrx	r3,0,r5
	li      r3, 0x0002      /* Add offset -- this register is 2 bytes */
	lhbrx   r4, r3, r6
	sync
	ori     r4, r4, 0xffff     	/* Clear all bits */
	sthbrx  r4, r3, r6
	sync
	lwbrx  r4,0,r6
	sync

	/*
	 * SDRAM initialization code for the Sandpoint board
         */

	LOADPTR (r3, MPC107_PICR1_ADRS) /* Get PICR1 bits */
	stwbrx	r3,0,r5
        sync
	lwbrx	r4,0,r6
	lis	r0, MPC107_PICR1_ROBITS_16
	ori	r0,r0, MPC107_PICR1_ROBITS_00
	and	r4,r4,r0	      /* preserve POR bits */

	LOADPTR (r0, MPC107_PICR1_VAL)
	or      r4, r4, r0
	stwbrx  r4,0,r6
	sync
	lwbrx   r4,0,r6
	sync

	LOADPTR (r3, MPC107_PICR2_ADRS)
	stwbrx  r3,0,r5
	LOADPTR (r0, MPC107_PICR2_VAL)
	stwbrx  r4,0,r6
	sync
	lwbrx   r4,0,r6
	sync

	LOADPTR (r3, MPC107_MCCR1_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MCCR1_VAL)	/* write default MCCR1 */
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_MCCR2_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MCCR2_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_MCCR3_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MCCR3_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_MCCR4_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MCCR4_VAL)
	stwbrx r4,0,r6
	sync

	LOADPTR (r3, MPC107_MSAR1_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MSAR1_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_MSAR2_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MSAR2_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_XMSAR1_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_XMSAR1_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_XMSAR2_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_XMSAR2_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_MEAR1_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MEAR1_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_MEAR2_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_MEAR2_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_XMEAR1_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_XMEAR1_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_XMEAR2_ADRS)
	stwbrx r3,0,r5
	LOADPTR (r4, MPC107_XMEAR2_VAL)
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	LOADPTR (r3, MPC107_ODCR_ADRS)		/* Set ODCR */
	stwbrx r3,0,r5
	sync

    	lbz    r4, 3(r6)           	/* read current register state */
	li     r4, 0x00ff          	/* default setting */
	stb    r4, 3(r6)           	/* New settings. */

	/*
	 * The MPC106 Manual states M106_MBER_ADRS == M106_CFG_BASE + 0xa0,
         * and that M106_MPMR_ADRS == M106_CFG_BASE + 0xa3.
         * Interestingly, Both Dink32 and the MPC106 manual access both
         * 8 bit (offset 0xa0 and 0xa3) registers in one 32bit operation,
         * using stwbrx, which is questionable since they are eight bit
         * registers.  It seems proper to access eight bit regiters with
         * stbx, however to match the convention of Motorola Dink32 and
         * the MPC106 manual code, both are written together with stwbrx.
	 */

	/* Enable memory banks and setup PAGE mode for SDRAM */

	LOADPTR (r3, MPC107_MBER_ADRS)
	stwbrx r3,0,r5
	addis  r4,r0,MPC107_MPMR_VAL
	ori    r4,r4,MPC107_MBER_VAL
	stwbrx r4,0,r6
	sync
	lwbrx  r4,0,r6
	sync

	/* Wait before initialize other registers */
	/*
	 * Adding a "nop" to the loop, and increasing count from 0x3800
	 * to 0x7000, for 7400 (400MHz).  No idea how much headroom this
	 * leaves for faster processors :)
	 */
	li	r4,0x7000
	mtctr   r4

Wait200us:
	nop
	bdnz	Wait200us


	/* Set MEMGO bit */

	LOADPTR (r3, MPC107_MCCR1_ADRS)
	stwbrx r3,0,r5
	sync
	lwbrx  r4,0,r6			/* old MCCR1 */
	addis  r3,r0,0x0008
	ori    r3,r3,0x0000
	or     r4,r4,r3			/* set bits */
	stwbrx  r4,0,r6
	sync
	lwbrx  r4,0,r6			/* read in just to check */

	/* Wait again */
	/*
	 * As above, double the count (8000 => 16000) and add a nop for
	 * the 400MHz 7400.  Good luck, you'll need it :)
	 */

	li	r4, 16000
	mtctr	r4

Wait8ref:
	nop
	bdnz	Wait8ref

	sync

	b	startCSetup	/* now do mmu setup for processor */


startCSetup:

#if	FALSE	/* EABI SDA not supported yet */

        /* initialize r2 and r13 according to EABI standard */

	LOADPTR (r2, _SDA2_BASE_)
	LOADPTR (r13, _SDA_BASE_)

#endif	/* FALSE */

	/* go to C entry point */

	or	r3, r11, r11		/* put startType in r3 (p0) */
	addi	sp, sp, -FRAMEBASESZ	/* save one frame stack */

	LOADPTR (r6, romStart)
	LOADPTR (r7, romInit)
	LOADPTR (r8, ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8

	mtlr	r6		/* romStart - romInit + ROM_TEXT_ADRS */
	blr
FUNC_END(romInit)