startup.s

rs485的通信程序的主程序。采用at91sam7a3芯片编写的。

/***********************************************************************/
/*  This file is part of the CA ARM C Compiler package                 */
/*  Copyright KEIL ELEKTRONIK GmbH 2002-2004                           */
/***********************************************************************/
/*                                                                     */
/*  STARTUP.S:  Startup file for Atmel AT91 device series              */
/*                                                                     */
/***********************************************************************/


/* 
//*** <<< Use Configuration Wizard in Context Menu >>> *** 
*/


// *** Startup Code (executed after Reset) ***


// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

        Mode_USR  EQU      0x10
        Mode_FIQ  EQU      0x11
        Mode_IRQ  EQU      0x12
        Mode_SVC  EQU      0x13
        Mode_ABT  EQU      0x17
        Mode_UND  EQU      0x1B
        Mode_SYS  EQU      0x1F

        I_Bit     EQU      0x80    /* when I bit is set, IRQ is disabled */
        F_Bit     EQU      0x40    /* when F bit is set, FIQ is disabled */


// Internal RAM Address
        RAM_Base  EQU      0x00000000  ; after Remap
        RAM_Boot  EQU      0x00300000  ; after Reset until Remap 


/*
// <h> Stack Configuration (Stack Sizes in Bytes)
//   <o0> Undefined Mode      <0x0-0xFFFFFFFF>
//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF>
//   <o2> Abort Mode          <0x0-0xFFFFFFFF>
//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF>
//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF>
//   <o5> User/System Mode    <0x0-0xFFFFFFFF>
// </h>
*/
        UND_Stack_Size  EQU     0x00000004
        SVC_Stack_Size  EQU     0x00000004
        ABT_Stack_Size  EQU     0x00000004
        FIQ_Stack_Size  EQU     0x00000004
        IRQ_Stack_Size  EQU     0x00000080
        USR_Stack_Size  EQU     0x00000400

AREA   STACK, DATA, READWRITE, ALIGN=2
        DS   (USR_Stack_Size+3)&~3  ; Stack for User/System Mode 
        DS   (IRQ_Stack_Size+3)&~3  ; Stack for Interrupt Mode
        DS   (FIQ_Stack_Size+3)&~3  ; Stack for Fast Interrupt Mode 
        DS   (ABT_Stack_Size+3)&~3  ; Stack for Abort Mode
        DS   (SVC_Stack_Size+3)&~3  ; Stack for Supervisor Mode
        DS   (UND_Stack_Size+3)&~3  ; Stack for Undefined Mode
Top_Stack:


/*
// <h> External Bus Interface (EBI)
*/
        EBI_BASE        EQU     0xFFE00000

/*
//   <e.13> Enable Chip Select 0 (CSR0)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR0_Val    EQU     0x010024A9

/*
//   <e.13> Enable Chip Select 1 (CSR1)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR1_Val    EQU     0x040034A5

/*
//   <e.13> Enable Chip Select 2 (CSR2)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR2_Val    EQU     0x20000000

/*
//   <e.13> Enable Chip Select 3 (CSR3)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR3_Val    EQU     0x30000000

/*
//   <e.13> Enable Chip Select 4 (CSR4)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR4_Val    EQU     0x40000000

/*
//   <e.13> Enable Chip Select 5 (CSR5)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR5_Val    EQU     0x50000000

/*
//   <e.13> Enable Chip Select 6 (CSR6)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR6_Val    EQU     0x60000000

/*
//   <e.13> Enable Chip Select 7 (CSR7)
//     <o.20..31> BA: Base Address <0x0-0xFFF00000:0x100000><#/0x100000>
//                <i> Start Address for Chip Select Signal
//     <o.7..8>   PAGES: Page Size      <0=> 1M Byte    <1=> 4M Bytes
//                                      <2=> 16M Bytes  <3=> 64M Bytes
//                <i> Selects Active Bits in Base Address
//     <o.0..1>   DBW: Data Bus Width   <1=> 16-bit     <2=> 8-bit
//     <o.12>     BAT: Byte Access Type <0=> Byte-write
//                                      <1=> Byte-select
//     <e.5>      WSE: Enable Wait State Generation
//       <o.2..4>   NWS: Number of Standard Wait States <1-8><#-1>
//     </e>
//     <o.9..11>  TDF: Data Float Output Time <0-7>
//                <i> Number of Cycles Added after the Transfer
//   </e>
*/
        EBI_CSR7_Val    EQU     0x70000000

/*
//   <q.4>        DRP: Data Read Protocol
//                     <0=> Standard Read
//                     <1=> Early Read
*/
        EBI_MCR_Val     EQU     0x00000010

/*
// </h> End of EBI
*/


// AT91M42800A Power Mangement Controller (PMC) definitions
        PMC_BASE        EQU     0xFFFF4000  /* PMC Base Address */
        PMC_CGMR        EQU     0x20        /* PMC_CGMR Offset */
        PMC_SR          EQU     0x30        /* PMC_SR Offset */
        PMC_MCKOSS      EQU     (3<<4)      /* Master Clock Output Selection */
        PMC_MCKO        EQU     (1<<6)      /* Master Clock Output Disable */
        PMC_PLLS        EQU     (1<<3)      /* PLL Selection */
        PMC_CSS         EQU     (1<<7)      /* Clock Source Selection */
        PMC_PRES        EQU     (7<<0)      /* Prescaler Selection */
        PMC_MUL         EQU     (0x7FF<<8)  /* Phase Lock Loop Factor */
        PMC_PLLCOUNT    EQU     (0xFF<<24)  /* PLL Lock Counter */
        PMC_PLL_LOCK    EQU     (1<<0)      /* PLL Lock Status */

/*
// <e> AT91M42800A PMC Clock Setup
//   <o1.7>      CSS: Clock Source Selection
//               <0=> Slow Clock
//               <1=> PLL Output
//   <o1.3>      PLLS: PLL Selection
//               <0=> PLL A (5 - 20MHz)
//               <1=> PLL B (20 - 80MHz)
//   <o1.0..2>   PRES: Prescaler
//               <0=> None
//               <1=> Clock / 2    <2=> Clock / 4
//               <3=> Clock / 8    <4=> Clock / 16
//               <5=> Clock / 32   <6=> Clock / 64
//   <o1.8..18>  MUL: Phase Lock Loop Factor <0-2047>
//               <i> PLL Output is multiplied by MUL+1
//   <o1.24..31> PLLCOUNT: PLL Lock Counter <0x0-0xFF>
//               <i> PLL Lock Timer
//   <o1.4..5>   MCKOSS: Master Clock Output Source Selection
//               <0=> Slow Clock
//               <1=> Master Clock
//               <2=> Master Clock Inverted