drcparams_dv34.c

Zoran V966 DVD 解码 Soc芯片的源程序

   PARAMS_TERMINATOR
};

CONST DrcParam DrcDVDNbcaSearchParams[] = {
   {0xa03,                                0x4A73}, // DSP (0x4a73): set RF channel resistance to 80kohm
   {0xa05,                                0x0180}, // DSP (0x180): set RF_Offset for saturation
   {0xa45,                                0x2505}, // DSP (0x2505): freeze RF AGC while defect and use Agc_Meter_Alpha=5
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDGParams[] = {
// Drc generel parameters for all kinds of CDs
   {ADC_Dig_Offset_RF,                    0x0000}, // DSP (0x0000)
   {ADC_Dig_Offset_RF_Shadow,             0x0000}, // DSP (0x0000)
   {DRC_Clock_Enable,                     0x0388}, // DSP (0x0388)
   {DRC_DPLL_Freq_Ratio_Initial_Value_LSB,   0x0333}, // DSP (0x0333): DPLL Freq Ratio Init LS
   {DRC_Viterbi_Peak_Limiter_And_Memory_Depth,   0x021F}, // DSP (0x021f): * same as DVDGParam *
   {DRC_Viterbi_Const___01_16__2_5__10_07,   0x7DAD}, // DSP (0x7dad): * same as DVDGParam *
   {DRC_Viterbi_Const_11_06__3_4,         0x03ED}, // DSP (0x03ed): * same as DVDGParam *
   {DRC_Viterbi_Const16_5_7,              0x7DAD}, // DSP (0x7dad): * same as DVDGParam *
   {DRC_Viterbi_Const6_4_Pit,             0x03ED}, // DSP (0x03ed): * same as DVDGParam *
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDSParams[] = {
// Drc parameters for CDs
   {DRC_DPLL_Freq_Ratio_Initial_Value_MSB,   0x001F}, // DSP (0x001f): DPLL Freq Ratio Init MS
   {DRC_Global_Programming,               0x0001}, // DSP (0x0001): * same as DVDGParam *
   {DRC_DPLL_Global_Programming,          0xF028}, // DSP (0xf028): DPLL: 'CD'; Enable DPLL NB; Init DPLL; Round width to nearest; Time Out Counter = 3; Enable Timeout
   {DRC_Equalizer_Programming,            0x1800}, // DSP (0x1800): * same as DVDGParam *
   {DRC_Coef0817_Programming,             0x0000}, // DSP (0x0000): * same as DVDGParam *
   {DRC_Coef2635_Programming,             0x008F}, // DSP (0x008f): * same as DVDGParam *
   {DRC_Coef4_Programming,                0x803E}, // DSP (0x803e): * same as DVDGParam *
   {DRC_Infilter,                         0x0001}, // DSP (0x0001): * same as DVDGParam *
   {DRC_Equalizer_HPF,                    0x8880}, // DSP (0x8880): * same as DVDGParam *
   {DRC_Threshold_Programming,            0x0064}, // DSP (0x0064): Use the fix for I96B;Threshold: ThBW = 5 ; Int Gain = 13;
   {DRC_DPLL_Filter_Wide_Band,            0x5520}, // DSP (0x5520): DPLL_WB KintegralNW = 0; ProGain = 1; IntGain = 5; Kv = 5
   {DRC_DPLL_Filter_Narrow_Band,          0x5520}, // DSP (0x5520): DPLL_NB KvN-Kv = 0; ProGainN = 2; IntGainN = 5; KvN = 5
   {DRC_DPLL_Filter_Minimum_Width,        0x0303}, // DSP (0x0303): * same as DVDGParam *
   {DRC_DPLL_Invalid_Sync,                0x03FF}, // DSP (0x03ff): * same as DVDGParam *
   {DRC_DPLL_Number_Of_Good_Frame_For_NB,   0x0041}, // DSP (0x0041): * same as DVDGParam *
   {DRC_DPLL_Frame_Window,                0x01B9}, // DSP (0x01b9): DPLL Frame Sync Window: Frame Sync Window = 441
   {DRC_Phase_Lock_Error_Init,            0x1964}, // DSP (0x1964): * same as DVDGParam *
   {DRC_Phase_Unlock_Error_Max,           0x1900}, // DSP (0x1900): * same as DVDGParam *
   {DRC_Phase_Lock_Error_Min,             0x189C}, // DSP (0x189c): * same as DVDGParam *
   {DRC_Phase_Lock_Total_Error_Max_Ramp_Detector_Max,   0x2050}, // DSP (0x2050): * same as DVDGParam *
// Defect_CDG_Params
   {Defect_Ctrl,                          0x0004}, // DSP (0x0004): Defect clock = 67.5MHz clock ; use AC coupled RF (Equalizer output); Defect mode - black dot OR white dot
   {Defect_Peak_Time1,                    0x0040}, // DSP (0x40)
   {Defect_Peak_Time2,                    0x0080}, // DSP (0x80)
   {Srv_Defect_Peak_Time1,                0x0040}, // DSP (0x40)
   {Srv_Defect_Peak_Time2,                0x0080}, // DSP (0x80)
   {Defect_Parameters,                    0x8048}, // DSP (0x8048): Defect Enable ; Defect Threshold = 0x10
   {Defect_Delay,                         0x0200}, // DSP (0x0200): Defect Delay = 0x200
   {WD_Parameters,                        0x0000}, // DSP (0x0000): WD Defect Enable ; WD Defect Threshold = 0x10
// AGC_DVDG_Params
   {AGC_Params0,                          0x0080}, // DSP (0x0080): peak detector window length (100 samples)
   {AGC_Params1,                          0x0080}, // DSP (0x0080): sat detector window length (100 samples)
   {AGC_Params2,                          0x1044}, // DSP (0x1044): acc.width (0x1), gain up (0x1) and down (0x4) steps
   {AGC_Params3,                          0x003C}, // DSP (0x003c): max of RF signal
   {AGC_Params4,                          0x0034}, // DSP (0x0034): min of RF signal
   {AGC_Control,                          0x2807}, // DSP (0x2807)
   {DRC_Freq_Delta,                       0x0065}, // DSP (0x0065): Freq Det Max Delat = 101
   {DRC_Global_Programming,               0x0000}, // DSP (0x0000): * same as DVDGParam *
   {DRC_DPLL_Global_Programming,          0xF0C8}, // DSP (0xf0c8): DPLL: 'DVD'; Enable DPLL NB; elease DPLL; No Freeze; Lock Mode = Freq&Phase; Round width to nearest; Time Out Counter = 3; Enable Timeout
   {DRC_Defect_Programming,               0x0070}, // DSP (0x0070): * same as DVDGParam *
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDRWSParams[] = {
// Drc parameters for CDRWs
   {DRC_DPLL_Freq_Ratio_Initial_Value_MSB,   0x0036}, // DSP (0x0036): DPLL Freq Ratio Init MS
   {DRC_Global_Programming,               0x0001}, // DSP (0x0001): * same as DrcCDGParams *
   {DRC_DPLL_Global_Programming,          0xF028}, // DSP (0xf028): * same as DrcCDGParams *
   {DRC_Equalizer_Programming,            0x1800}, // DSP (0x1800): * same as DrcCDGParams *
   {DRC_Coef0817_Programming,             0x0000}, // DSP (0x0000): * same as DrcCDGParams *
   {DRC_Coef2635_Programming,             0x0088}, // DSP (0x0088): * same as DrcCDGParams *
   {DRC_Coef4_Programming,                0x8030}, // DSP (0x8030): * same as DrcCDGParams *
   {DRC_Infilter,                         0x0001}, // DSP (0x0001): * same as DrcCDGParams *
   {DRC_Equalizer_HPF,                    0x8A80}, // DSP (0x8a80): * same as DrcCDGParams *
   {DRC_Threshold_Programming,            0x00D5}, // DSP (0x00d5): Use the fix for I96B;* same as DrcCDGParams *
   {DRC_DPLL_Filter_Wide_Band,            0x7541}, // DSP (0x7541): DPLL_WB KintegralNW = 1; ProGain = 2; IntGain = 5; Kv = 7
   {DRC_DPLL_Filter_Narrow_Band,          0x8541}, // DSP (0x8541): DPLL_NB KvN-Kv = 1; ProGainN = 4; IntGainN = 5; KvN = 8
   {DRC_DPLL_Filter_Minimum_Width,        0x0303}, // DSP (0x0303): * same as DrcCDGParams *
   {DRC_DPLL_Invalid_Sync,                0x03FF}, // DSP (0x03ff): * same as DrcCDGParams *
   {DRC_DPLL_Number_Of_Good_Frame_For_NB,   0x0041}, // DSP (0x0041): * same as DrcCDGParams *
   {DRC_DPLL_Frame_Window,                0x01B9}, // DSP (0x01b9): * same as DrcCDGParams *
   {DRC_Phase_Lock_Error_Init,            0x1964}, // DSP (0x1964): * same as DrcCDGParams *
   {DRC_Phase_Unlock_Error_Max,           0x1900}, // DSP (0x1900): * same as DrcCDGParams *
   {DRC_Phase_Lock_Error_Min,             0x189C}, // DSP (0x189c): * same as DrcCDGParams *
   {DRC_Phase_Lock_Total_Error_Max_Ramp_Detector_Max,   0x3050}, // DSP (0x3050): * same as DrcCDGParams *
// Defect_CDRWG_Params
   {Defect_Ctrl,                          0x0000}, // DSP (0x0000): Defect clock = PLL clock ; use DC coupled RF ; Defect mode - black dot OR white dot
   {Defect_Peak_Time1,                    0x0040}, // DSP (0x40)
   {Defect_Peak_Time2,                    0x0080}, // DSP (0x80)
   {Srv_Defect_Peak_Time1,                0x0040}, // DSP (0x40)
   {Srv_Defect_Peak_Time2,                0x0080}, // DSP (0x80)
   {Defect_Parameters,                    0x8098}, // DSP (0x8098): Defect Enable ; Defect Threshold = 0x10
   {Defect_Delay,                         0x0200}, // DSP (0x0200): Defect Delay = 0x200
   {WD_Parameters,                        0x0000}, // DSP (0x0000): WD Defect Enable ; WD Defect Threshold = 0x10
// AGC_CDRWG_Params
   {AGC_Params0,                          0x0080}, // DSP (0x0080): peak detector window length (100 samples)
   {AGC_Params1,                          0x0080}, // DSP (0x0080): sat detector window length (100 samples)
   {AGC_Params2,                          0x1044}, // DSP (0x1044): acc.width (0x1), gain up (0x1) and down (0x4) steps
   {AGC_Params3,                          0x003C}, // DSP (0x003c): max of RF signal
   {AGC_Params4,                          0x0034}, // DSP (0x0034): min of RF signal
   {AGC_Control,                          0x2807}, // DSP (0x2807)
   {DRC_Freq_Delta,                       0x0065}, // DSP (0x0065): * same as DrcCDGParams *
   {DRC_Global_Programming,               0x0000}, // DSP (0x0000): * same as DrcCDGParams *
   {DRC_DPLL_Global_Programming,          0xF0C8}, // DSP (0xf0c8): * same as DrcCDGParams *
   {DRC_Defect_Programming,               0x0070}, // DSP (0x0070): * same as DrcCDGParams *
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDDefaultParams[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7560}, // DSP (0x7560)
   {DRC_DPLL_Filter_Narrow_Band,          0x7580}, // DSP (0x7580)
   {DRC_Infilter,                         0x8000}, // DSP (0x8000)
   {Defect_Parameters,                    0x80C0}, // DSP (0x80c0)
   {DRC_Coef0817_Programming,             0x0000}, // DSP (0x0000)
   {DRC_Coef2635_Programming,             0x0090}, // DSP (0x0090)
   {DRC_Coef4_Programming,                0x8040}, // DSP (0x8040)
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDRWDefaultParams[] = {
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDDefect1Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7560}, // DSP (0x7560)
   {DRC_DPLL_Filter_Narrow_Band,          0x7580}, // DSP (0x7580)
   {DRC_Infilter,                         0x8000}, // DSP (0x8000)
   {Defect_Parameters,                    0x80C0}, // DSP (0x80c0)
   {DRC_Coef0817_Programming,             0x0000}, // DSP (0x0000)
   {DRC_Coef2635_Programming,             0x0090}, // DSP (0x0090)
   {DRC_Coef4_Programming,                0x8040}, // DSP (0x8040)
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDRWDefect1Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7540}, // DSP (0x7540): DPLL_WB KintegralNW = 0; ProGain = 2; IntGain = 5; Kv = 7
   {DRC_DPLL_Filter_Narrow_Band,          0x7540}, // DSP (0x7540): DPLL_NB KvN-Kv = 0; ProGainN = 4; IntGainN = 5; KvN = 7
   {DRC_Equalizer_Programming,            0x1800}, // DSP (0x1800): Enable Equalizer's LPF
   {DRC_Infilter,                         0x0001}, // DSP (0x0001): Use InFilter
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDDefect2Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x5520}, // DSP (0x5520)
   {DRC_DPLL_Filter_Narrow_Band,          0x5520}, // DSP (0x5520)
   {DRC_Infilter,                         0x8000}, // DSP (0x8000)
   {Defect_Parameters,                    0x8048}, // DSP (0x8048)
   {DRC_Coef0817_Programming,             0x0000}, // DSP (0x0000)
   {DRC_Coef2635_Programming,             0x008F}, // DSP (0x008f)
   {DRC_Coef4_Programming,                0x803E}, // DSP (0x803e)
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDRWDefect2Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7540}, // DSP (0x7540): DPLL_WB KintegralNW = 0; ProGain = 2; IntGain = 5; Kv = 7
   {DRC_DPLL_Filter_Narrow_Band,          0x7540}, // DSP (0x7540): DPLL_NB KvN-Kv = 0; ProGainN = 4; IntGainN = 5; KvN = 7
   {DRC_Equalizer_Programming,            0x1800}, // DSP (0x1800): Enable Equalizer's LPF
   {DRC_Infilter,                         0x0001}, // DSP (0x0001): Use InFilter
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDHighJitter1Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7541}, // DSP (0x7541): DPLL_WB KintegralNW = 1; ProGain = 2; IntGain = 5; Kv = 7
   {DRC_DPLL_Filter_Narrow_Band,          0x8541}, // DSP (0x8541): DPLL_NB KvN-Kv = 1; ProGainN = 4; IntGainN = 5; KvN = 8
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDRWHighJitter1Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7541}, // DSP (0x7541): DPLL_WB KintegralNW = 1; ProGain = 2; IntGain = 5; Kv = 7
   {DRC_DPLL_Filter_Narrow_Band,          0x8541}, // DSP (0x8541): DPLL_NB KvN-Kv = 1; ProGainN = 4; IntGainN = 5; KvN = 8
   {DRC_Equalizer_Programming,            0x1800}, // DSP (0x1800): enable Equalizer's LPF
   {DRC_Infilter,                         0x0001}, // DSP (0x0001): Use InFilter
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDHighJitter2Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7560}, // DSP (0x7560): DPLL_WB KintegralNW = 0; ProGain = 3; IntGain = 5; Kv = 7
   {DRC_DPLL_Filter_Narrow_Band,          0x7580}, // DSP (0x7580): DPLL_NB KvN-Kv = 0; ProGainN = 8; IntGainN = 5; KvN = 7
   {DRC_Equalizer_Programming,            0x0800}, // DSP (0x0800): Disable Equalizer's LPF
   {DRC_Infilter,                         0x0001}, // DSP (0x0001): Use InFilter
   PARAMS_TERMINATOR
};

CONST DrcParam DrcCDRWHighJitter2Params[] = {
   {DRC_DPLL_Filter_Wide_Band,            0x7541}, // DSP (0x7541): DPLL_WB KintegralNW = 1; ProGain = 2; IntGain = 5; Kv = 7
   {DRC_DPLL_Filter_Narrow_Band,          0x8541}, // DSP (0x8541): DPLL_NB KvN-Kv = 1; ProGainN = 4; IntGainN = 5; KvN = 8
   {DRC_Equalizer_Programming,            0x1800}, // DSP (0x1800): enable Equalizer's LPF
   {DRC_Infilter,                         0x0001}, // DSP (0x0001): Use InFilter
   PARAMS_TERMINATOR
};