tlc5620.tan.qmsg

这是一个用vhdl写的控制VGA的源程序,可以显示6种不同的图案,你也可以显示图象

{ "Info" "ITDB_TH_RESULT" "data~reg0 rng clk -3.800 ns register " "Info: th for register \"data~reg0\" (data pin = \"rng\", clock pin = \"clk\") is -3.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_125 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ck 2 REG LC5_B31 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.900 ns" { clk ck } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.500 ns) 4.700 ns sload 3 REG LC1_B29 19 " "Info: 3: + IC(1.300 ns) + CELL(0.500 ns) = 4.700 ns; Loc. = LC1_B29; Fanout = 19; REG Node = 'sload'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.800 ns" { ck sload } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 7.300 ns daclk~0 4 COMB LC6_B31 2 " "Info: 4: + IC(1.000 ns) + CELL(1.600 ns) = 7.300 ns; Loc. = LC6_B31; Fanout = 2; COMB Node = 'daclk~0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.600 ns" { sload daclk~0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 8.600 ns data~reg0 5 REG LC8_B29 1 " "Info: 5: + IC(1.300 ns) + CELL(0.000 ns) = 8.600 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.300 ns" { daclk~0 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 53.49 % " "Info: Total cell delay = 4.600 ns ( 53.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 46.51 % " "Info: Total interconnect delay = 4.000 ns ( 46.51 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 1.300ns 1.000ns 1.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 1.600ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 13.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns rng 1 PIN PIN_72 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_72; Fanout = 1; PIN Node = 'rng'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { rng } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.700 ns) 9.800 ns Mux~704 2 COMB LC2_B36 1 " "Info: 2: + IC(3.200 ns) + CELL(1.700 ns) = 9.800 ns; Loc. = LC2_B36; Fanout = 1; COMB Node = 'Mux~704'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "4.900 ns" { rng Mux~704 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 12.600 ns Mux~705 3 COMB LC5_B29 1 " "Info: 3: + IC(1.200 ns) + CELL(1.600 ns) = 12.600 ns; Loc. = LC5_B29; Fanout = 1; COMB Node = 'Mux~705'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.800 ns" { Mux~704 Mux~705 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 13.700 ns data~reg0 4 REG LC8_B29 1 " "Info: 4: + IC(0.300 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.100 ns" { Mux~705 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 65.69 % " "Info: Total cell delay = 9.000 ns ( 65.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 34.31 % " "Info: Total interconnect delay = 4.700 ns ( 34.31 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "13.700 ns" { rng Mux~704 Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "13.700 ns" { rng rng~out Mux~704 Mux~705 data~reg0 } { 0.000ns 0.000ns 3.200ns 1.200ns 0.300ns } { 0.000ns 4.900ns 1.700ns 1.600ns 0.800ns } } }  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 1.300ns 1.000ns 1.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 1.600ns 0.000ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "13.700 ns" { rng Mux~704 Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "13.700 ns" { rng rng~out Mux~704 Mux~705 data~reg0 } { 0.000ns 0.000ns 3.200ns 1.200ns 0.300ns } { 0.000ns 4.900ns 1.700ns 1.600ns 0.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 15 10:38:05 2006 " "Info: Processing ended: Thu Jun 15 10:38:05 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}