tlc5620.tan.qmsg

这是一个用vhdl写的控制VGA的源程序,可以显示6种不同的图案,你也可以显示图象

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 5 " "Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] data~reg0 clk 2.6 ns " "Info: Found hold time violation between source  pin or register \"lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]\" and destination pin or register \"data~reg0\" for clock \"clk\" (Hold time is 2.6 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.400 ns + Largest " "Info: + Largest clock skew is 5.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_125 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ck 2 REG LC5_B31 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.900 ns" { clk ck } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.500 ns) 4.700 ns sload 3 REG LC1_B29 19 " "Info: 3: + IC(1.300 ns) + CELL(0.500 ns) = 4.700 ns; Loc. = LC1_B29; Fanout = 19; REG Node = 'sload'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.800 ns" { ck sload } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 7.300 ns daclk~0 4 COMB LC6_B31 2 " "Info: 4: + IC(1.000 ns) + CELL(1.600 ns) = 7.300 ns; Loc. = LC6_B31; Fanout = 2; COMB Node = 'daclk~0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.600 ns" { sload daclk~0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 8.600 ns data~reg0 5 REG LC8_B29 1 " "Info: 5: + IC(1.300 ns) + CELL(0.000 ns) = 8.600 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.300 ns" { daclk~0 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 53.49 % " "Info: Total cell delay = 4.600 ns ( 53.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 46.51 % " "Info: Total interconnect delay = 4.000 ns ( 46.51 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload daclk~0 data~reg0 } { 0.0ns 0.0ns 0.4ns 1.3ns 1.0ns 1.3ns } { 0.0ns 2.0ns 0.5ns 0.5ns 1.6ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_125 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ck 2 REG LC5_B31 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.900 ns" { clk ck } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 3.200 ns lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 3 REG LC3_B31 7 " "Info: 3: + IC(0.300 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC3_B31; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.300 ns" { ck lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 78.13 % " "Info: Total cell delay = 2.500 ns ( 78.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns 21.88 % " "Info: Total interconnect delay = 0.700 ns ( 21.88 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "3.200 ns" { clk ck lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out ck lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.0ns 0.0ns 0.4ns 0.3ns } { 0.0ns 2.0ns 0.5ns 0.0ns } } }  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload daclk~0 data~reg0 } { 0.0ns 0.0ns 0.4ns 1.3ns 1.0ns 1.3ns } { 0.0ns 2.0ns 0.5ns 0.5ns 1.6ns 0.0ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "3.200 ns" { clk ck lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out ck lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.0ns 0.0ns 0.4ns 0.3ns } { 0.0ns 2.0ns 0.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns - " "Info: - Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns - Shortest register register " "Info: - Shortest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 1 REG LC3_B31 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B31; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.400 ns) 2.500 ns Mux~705 2 COMB LC5_B29 1 " "Info: 2: + IC(1.100 ns) + CELL(1.400 ns) = 2.500 ns; Loc. = LC5_B29; Fanout = 1; COMB Node = 'Mux~705'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.500 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Mux~705 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 3.600 ns data~reg0 3 REG LC8_B29 1 " "Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 3.600 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.100 ns" { Mux~705 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 61.11 % " "Info: Total cell delay = 2.200 ns ( 61.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 38.89 % " "Info: Total interconnect delay = 1.400 ns ( 38.89 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "3.600 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Mux~705 data~reg0 } { 0.0ns 1.1ns 0.3ns } { 0.0ns 1.4ns 0.8ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload daclk~0 data~reg0 } { 0.0ns 0.0ns 0.4ns 1.3ns 1.0ns 1.3ns } { 0.0ns 2.0ns 0.5ns 0.5ns 1.6ns 0.0ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "3.200 ns" { clk ck lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out ck lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.0ns 0.0ns 0.4ns 0.3ns } { 0.0ns 2.0ns 0.5ns 0.0ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "3.600 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2] Mux~705 data~reg0 } { 0.0ns 1.1ns 0.3ns } { 0.0ns 1.4ns 0.8ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "data~reg0 a0 clk 10.100 ns register " "Info: tsu for register \"data~reg0\" (data pin = \"a0\", clock pin = \"clk\") is 10.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.400 ns + Longest pin register " "Info: + Longest pin to register delay is 15.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns a0 1 PIN PIN_68 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_68; Fanout = 1; PIN Node = 'a0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { a0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.600 ns) 9.600 ns Mux~703 2 COMB LC4_B36 1 " "Info: 2: + IC(3.100 ns) + CELL(1.600 ns) = 9.600 ns; Loc. = LC4_B36; Fanout = 1; COMB Node = 'Mux~703'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "4.700 ns" { a0 Mux~703 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 11.500 ns Mux~704 3 COMB LC2_B36 1 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 11.500 ns; Loc. = LC2_B36; Fanout = 1; COMB Node = 'Mux~704'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.900 ns" { Mux~703 Mux~704 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 14.300 ns Mux~705 4 COMB LC5_B29 1 " "Info: 4: + IC(1.200 ns) + CELL(1.600 ns) = 14.300 ns; Loc. = LC5_B29; Fanout = 1; COMB Node = 'Mux~705'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.800 ns" { Mux~704 Mux~705 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 15.400 ns data~reg0 5 REG LC8_B29 1 " "Info: 5: + IC(0.300 ns) + CELL(0.800 ns) = 15.400 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.100 ns" { Mux~705 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.500 ns 68.18 % " "Info: Total cell delay = 10.500 ns ( 68.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns 31.82 % " "Info: Total interconnect delay = 4.900 ns ( 31.82 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "15.400 ns" { a0 Mux~703 Mux~704 Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "15.400 ns" { a0 a0~out Mux~703 Mux~704 Mux~705 data~reg0 } { 0.000ns 0.000ns 3.100ns 0.300ns 1.200ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.600ns 1.600ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_125 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ck 2 REG LC5_B31 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.900 ns" { clk ck } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 4.600 ns daclk~0 3 COMB LC6_B31 2 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 4.600 ns; Loc. = LC6_B31; Fanout = 2; COMB Node = 'daclk~0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.700 ns" { ck daclk~0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 5.900 ns data~reg0 4 REG LC8_B29 1 " "Info: 4: + IC(1.300 ns) + CELL(0.000 ns) = 5.900 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.300 ns" { daclk~0 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 66.10 % " "Info: Total cell delay = 3.900 ns ( 66.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 33.90 % " "Info: Total interconnect delay = 2.000 ns ( 33.90 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "5.900 ns" { clk ck daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { clk clk~out ck daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 0.300ns 1.300ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } }  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "15.400 ns" { a0 Mux~703 Mux~704 Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "15.400 ns" { a0 a0~out Mux~703 Mux~704 Mux~705 data~reg0 } { 0.000ns 0.000ns 3.100ns 0.300ns 1.200ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.600ns 1.600ns 0.800ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "5.900 ns" { clk ck daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { clk clk~out ck daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 0.300ns 1.300ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data data~reg0 16.100 ns register " "Info: tco from clock \"clk\" to destination pin \"data\" through register \"data~reg0\" is 16.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_125 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ck 2 REG LC5_B31 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.900 ns" { clk ck } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.500 ns) 4.700 ns sload 3 REG LC1_B29 19 " "Info: 3: + IC(1.300 ns) + CELL(0.500 ns) = 4.700 ns; Loc. = LC1_B29; Fanout = 19; REG Node = 'sload'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.800 ns" { ck sload } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 7.300 ns daclk~0 4 COMB LC6_B31 2 " "Info: 4: + IC(1.000 ns) + CELL(1.600 ns) = 7.300 ns; Loc. = LC6_B31; Fanout = 2; COMB Node = 'daclk~0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.600 ns" { sload daclk~0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 8.600 ns data~reg0 5 REG LC8_B29 1 " "Info: 5: + IC(1.300 ns) + CELL(0.000 ns) = 8.600 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.300 ns" { daclk~0 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 53.49 % " "Info: Total cell delay = 4.600 ns ( 53.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 46.51 % " "Info: Total interconnect delay = 4.000 ns ( 46.51 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 1.300ns 1.000ns 1.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 1.600ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest register pin " "Info: + Longest register to pin delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data~reg0 1 REG LC8_B29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(6.300 ns) 7.000 ns data 2 PIN PIN_137 0 " "Info: 2: + IC(0.700 ns) + CELL(6.300 ns) = 7.000 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'data'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "7.000 ns" { data~reg0 data } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 90.00 % " "Info: Total cell delay = 6.300 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns 10.00 % " "Info: Total interconnect delay = 0.700 ns ( 10.00 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "7.000 ns" { data~reg0 data } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "7.000 ns" { data~reg0 data } { 0.000ns 0.700ns } { 0.000ns 6.300ns } } }  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 1.300ns 1.000ns 1.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 1.600ns 0.000ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "7.000 ns" { data~reg0 data } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "7.000 ns" { data~reg0 data } { 0.000ns 0.700ns } { 0.000ns 6.300ns } } }  } 0}