tlc5620.tan.qmsg

这是一个用vhdl写的控制VGA的源程序,可以显示6种不同的图案,你也可以显示图象

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "daclk~0 " "Info: Detected gated clock \"daclk~0\" as buffer" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 11 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "daclk~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "ck " "Info: Detected ripple clock \"ck\" as buffer" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ck" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "sload " "Info: Detected ripple clock \"sload\" as buffer" {  } { { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sload" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q\[2\] register data~reg0 68.49 MHz 14.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 68.49 MHz between source register \"q\[2\]\" and destination register \"data~reg0\" (period= 14.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.800 ns + Longest register register " "Info: + Longest register to register delay is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[2\] 1 REG LC2_B28 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B28; Fanout = 1; REG Node = 'q\[2\]'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { q[2] } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 2.800 ns Mux~698 2 COMB LC1_B23 1 " "Info: 2: + IC(1.200 ns) + CELL(1.600 ns) = 2.800 ns; Loc. = LC1_B23; Fanout = 1; COMB Node = 'Mux~698'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.800 ns" { q[2] Mux~698 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.700 ns) 5.700 ns Mux~699 3 COMB LC2_B29 1 " "Info: 3: + IC(1.200 ns) + CELL(1.700 ns) = 5.700 ns; Loc. = LC2_B29; Fanout = 1; COMB Node = 'Mux~699'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.900 ns" { Mux~698 Mux~699 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 7.700 ns Mux~702 4 COMB LC4_B29 1 " "Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 7.700 ns; Loc. = LC4_B29; Fanout = 1; COMB Node = 'Mux~702'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.000 ns" { Mux~699 Mux~702 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 9.700 ns Mux~705 5 COMB LC5_B29 1 " "Info: 5: + IC(0.300 ns) + CELL(1.700 ns) = 9.700 ns; Loc. = LC5_B29; Fanout = 1; COMB Node = 'Mux~705'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "2.000 ns" { Mux~702 Mux~705 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 10.800 ns data~reg0 6 REG LC8_B29 1 " "Info: 6: + IC(0.300 ns) + CELL(0.800 ns) = 10.800 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.100 ns" { Mux~705 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 69.44 % " "Info: Total cell delay = 7.500 ns ( 69.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns 30.56 % " "Info: Total interconnect delay = 3.300 ns ( 30.56 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "10.800 ns" { q[2] Mux~698 Mux~699 Mux~702 Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "10.800 ns" { q[2] Mux~698 Mux~699 Mux~702 Mux~705 data~reg0 } { 0.000ns 1.200ns 1.200ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.700ns 1.700ns 1.700ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.700 ns - Smallest " "Info: - Smallest clock skew is -2.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_125 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ck 2 REG LC5_B31 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.900 ns" { clk ck } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 4.600 ns daclk~0 3 COMB LC6_B31 2 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 4.600 ns; Loc. = LC6_B31; Fanout = 2; COMB Node = 'daclk~0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.700 ns" { ck daclk~0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 5.900 ns data~reg0 4 REG LC8_B29 1 " "Info: 4: + IC(1.300 ns) + CELL(0.000 ns) = 5.900 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.300 ns" { daclk~0 data~reg0 } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 66.10 % " "Info: Total cell delay = 3.900 ns ( 66.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 33.90 % " "Info: Total interconnect delay = 2.000 ns ( 33.90 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "5.900 ns" { clk ck daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { clk clk~out ck daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 0.300ns 1.300ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.600 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_125 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ck 2 REG LC5_B31 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "0.900 ns" { clk ck } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.500 ns) 4.700 ns sload 3 REG LC1_B29 19 " "Info: 3: + IC(1.300 ns) + CELL(0.500 ns) = 4.700 ns; Loc. = LC1_B29; Fanout = 19; REG Node = 'sload'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "1.800 ns" { ck sload } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 8.600 ns q\[2\] 4 REG LC2_B28 1 " "Info: 4: + IC(3.900 ns) + CELL(0.000 ns) = 8.600 ns; Loc. = LC2_B28; Fanout = 1; REG Node = 'q\[2\]'" {  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "3.900 ns" { sload q[2] } "NODE_NAME" } "" } } { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 34.88 % " "Info: Total cell delay = 3.000 ns ( 34.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns 65.12 % " "Info: Total interconnect delay = 5.600 ns ( 65.12 % )" {  } {  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload q[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload q[2] } { 0.000ns 0.000ns 0.400ns 1.300ns 3.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "5.900 ns" { clk ck daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { clk clk~out ck daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 0.300ns 1.300ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload q[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload q[2] } { 0.000ns 0.000ns 0.400ns 1.300ns 3.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "tlc5620.vhd" "" { Text "J:/EH2000/tlc5620/tlc5620.vhd" 60 -1 0 } }  } 0}  } { { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "10.800 ns" { q[2] Mux~698 Mux~699 Mux~702 Mux~705 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "10.800 ns" { q[2] Mux~698 Mux~699 Mux~702 Mux~705 data~reg0 } { 0.000ns 1.200ns 1.200ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.700ns 1.700ns 1.700ns 0.800ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "5.900 ns" { clk ck daclk~0 data~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { clk clk~out ck daclk~0 data~reg0 } { 0.000ns 0.000ns 0.400ns 0.300ns 1.300ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } } } { "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" "" { Report "J:/EH2000/tlc5620/db/tlc5620_cmp.qrpt" Compiler "tlc5620" "UNKNOWN" "V1" "J:/EH2000/tlc5620/db/tlc5620.quartus_db" { Floorplan "J:/EH2000/tlc5620/" "" "8.600 ns" { clk ck sload q[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { clk clk~out ck sload q[2] } { 0.000ns 0.000ns 0.400ns 1.300ns 3.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0}