tlc5620.tan.summary

这是一个用vhdl写的控制VGA的源程序,可以显示6种不同的图案,你也可以显示图象

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.100 ns
From           : a0
To             : data~reg0
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.100 ns
From           : data~reg0
To             : data
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.800 ns
From           : rng
To             : data~reg0
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 68.49 MHz ( period = 14.600 ns )
From           : q[2]
To             : data~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
To             : data~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 5

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 5

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