tlc5620.tan.rpt

这是一个用vhdl写的控制VGA的源程序,可以显示6种不同的图案,你也可以显示图象

+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -3.800 ns ; rng  ; data~reg0 ; clk      ;
; N/A           ; None        ; -5.400 ns ; a1   ; data~reg0 ; clk      ;
; N/A           ; None        ; -5.500 ns ; a0   ; data~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Jun 15 10:38:03 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tlc5620 -c tlc5620
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "daclk~0" as buffer
    Info: Detected ripple clock "ck" as buffer
    Info: Detected ripple clock "sload" as buffer
Info: Clock "clk" has Internal fmax of 68.49 MHz between source register "q[2]" and destination register "data~reg0" (period= 14.6 ns)
    Info: + Longest register to register delay is 10.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B28; Fanout = 1; REG Node = 'q[2]'
        Info: 2: + IC(1.200 ns) + CELL(1.600 ns) = 2.800 ns; Loc. = LC1_B23; Fanout = 1; COMB Node = 'Mux~698'
        Info: 3: + IC(1.200 ns) + CELL(1.700 ns) = 5.700 ns; Loc. = LC2_B29; Fanout = 1; COMB Node = 'Mux~699'
        Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 7.700 ns; Loc. = LC4_B29; Fanout = 1; COMB Node = 'Mux~702'
        Info: 5: + IC(0.300 ns) + CELL(1.700 ns) = 9.700 ns; Loc. = LC5_B29; Fanout = 1; COMB Node = 'Mux~705'
        Info: 6: + IC(0.300 ns) + CELL(0.800 ns) = 10.800 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'
        Info: Total cell delay = 7.500 ns ( 69.44 % )
        Info: Total interconnect delay = 3.300 ns ( 30.56 % )
    Info: - Smallest clock skew is -2.700 ns
        Info: + Shortest clock path from clock "clk" to destination register is 5.900 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'
            Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 4.600 ns; Loc. = LC6_B31; Fanout = 2; COMB Node = 'daclk~0'
            Info: 4: + IC(1.300 ns) + CELL(0.000 ns) = 5.900 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'
            Info: Total cell delay = 3.900 ns ( 66.10 % )
            Info: Total interconnect delay = 2.000 ns ( 33.90 % )
        Info: - Longest clock path from clock "clk" to source register is 8.600 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'
            Info: 3: + IC(1.300 ns) + CELL(0.500 ns) = 4.700 ns; Loc. = LC1_B29; Fanout = 19; REG Node = 'sload'
            Info: 4: + IC(3.900 ns) + CELL(0.000 ns) = 8.600 ns; Loc. = LC2_B28; Fanout = 1; REG Node = 'q[2]'
            Info: Total cell delay = 3.000 ns ( 34.88 % )
            Info: Total interconnect delay = 5.600 ns ( 65.12 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2]" and destination pin or register "data~reg0" for clock "clk" (Hold time is 2.6 ns)
    Info: + Largest clock skew is 5.400 ns
        Info: + Longest clock path from clock "clk" to destination register is 8.600 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'
            Info: 3: + IC(1.300 ns) + CELL(0.500 ns) = 4.700 ns; Loc. = LC1_B29; Fanout = 19; REG Node = 'sload'
            Info: 4: + IC(1.000 ns) + CELL(1.600 ns) = 7.300 ns; Loc. = LC6_B31; Fanout = 2; COMB Node = 'daclk~0'
            Info: 5: + IC(1.300 ns) + CELL(0.000 ns) = 8.600 ns; Loc. = LC8_B29; Fanout = 1; REG Node = 'data~reg0'
            Info: Total cell delay = 4.600 ns ( 53.49 % )
            Info: Total interconnect delay = 4.000 ns ( 46.51 % )
        Info: - Shortest clock path from clock "clk" to source register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC5_B31; Fanout = 7; REG Node = 'ck'
            Info: 3: + IC(0.300 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC3_B31; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
            Info: Total cell delay = 2.500 ns ( 78.13 % )
            Info: Total interconn