frequent.laf

来自「这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一」· LAF 代码 · 共 1,476 行 · 第 1/5 页

  NET G_863_Z0  SRC G_863_$1I35.Z0  DST count6_3.D0 ;
  NET G_863_$1N8  SRC G_863_$1I31.Z0  DST G_863_$1I35.A1 ;
  NET G_863_$1N6  SRC G_863_$1I25.Z0  DST G_863_$1I35.A0 ;
  NET G_863_$1N22  SRC G_863_$1I38.ZN0  DST G_863_$1I25.A1 ;
  NET G_864_Z0  SRC G_864_$1I35.Z0  DST count5_0.D0 ;
  NET G_864_$1N8  SRC G_864_$1I31.Z0  DST G_864_$1I35.A1 ;
  NET G_864_$1N6  SRC G_864_$1I25.Z0  DST G_864_$1I35.A0 ;
  NET G_864_$1N22  SRC G_864_$1I38.ZN0  DST G_864_$1I25.A1 ;
  NET G_865_Z0  SRC G_865_$1I35.Z0  DST count5_1.D0 ;
  NET G_865_$1N8  SRC G_865_$1I31.Z0  DST G_865_$1I35.A1 ;
  NET G_865_$1N6  SRC G_865_$1I25.Z0  DST G_865_$1I35.A0 ;
  NET G_865_$1N22  SRC G_865_$1I38.ZN0  DST G_865_$1I25.A1 ;
  NET G_866_Z0  SRC G_866_$1I35.Z0  DST count5_2.D0 ;
  NET G_866_$1N8  SRC G_866_$1I31.Z0  DST G_866_$1I35.A1 ;
  NET G_866_$1N6  SRC G_866_$1I25.Z0  DST G_866_$1I35.A0 ;
  NET G_866_$1N22  SRC G_866_$1I38.ZN0  DST G_866_$1I25.A1 ;
  NET G_867_Z0  SRC G_867_$1I35.Z0  DST count5_3.D0 ;
  NET G_867_$1N8  SRC G_867_$1I31.Z0  DST G_867_$1I35.A1 ;
  NET G_867_$1N6  SRC G_867_$1I25.Z0  DST G_867_$1I35.A0 ;
  NET G_867_$1N22  SRC G_867_$1I38.ZN0  DST G_867_$1I25.A1 ;
  NET G_868_Z0  SRC G_868_$1I35.Z0  DST count4_0.D0 ;
  NET G_868_$1N8  SRC G_868_$1I31.Z0  DST G_868_$1I35.A1 ;
  NET G_868_$1N6  SRC G_868_$1I25.Z0  DST G_868_$1I35.A0 ;
  NET G_868_$1N22  SRC G_868_$1I38.ZN0  DST G_868_$1I25.A1 ;
  NET G_869_Z0  SRC G_869_$1I35.Z0  DST count4_1.D0 ;
  NET G_869_$1N8  SRC G_869_$1I31.Z0  DST G_869_$1I35.A1 ;
  NET G_869_$1N6  SRC G_869_$1I25.Z0  DST G_869_$1I35.A0 ;
  NET G_869_$1N22  SRC G_869_$1I38.ZN0  DST G_869_$1I25.A1 ;
  NET G_840_Z0  SRC G_840_$1I35.Z0  DST un1_cout6_2_i_0_3.A0 ;
  NET G_840_$1N8  SRC G_840_$1I31.Z0  DST G_840_$1I35.A1 ;
  NET G_840_$1N6  SRC G_840_$1I25.Z0  DST G_840_$1I35.A0 ;
  NET G_840_$1N22  SRC G_840_$1I38.ZN0  DST G_840_$1I25.A1 ;
  NET G_841_Z0  SRC G_841_$1I35.Z0  DST cout0_0.D0 ;
  NET G_841_$1N8  SRC G_841_$1I31.Z0  DST G_841_$1I35.A1 ;
  NET G_841_$1N6  SRC G_841_$1I25.Z0  DST G_841_$1I35.A0 ;
  NET G_841_$1N22  SRC G_841_$1I38.ZN0  DST G_841_$1I25.A1 ;
  NET G_842_Z0  SRC G_842_$1I35.Z0  DST cout0_2.D0 ;
  NET G_842_$1N8  SRC G_842_$1I31.Z0  DST G_842_$1I35.A1 ;
  NET G_842_$1N6  SRC G_842_$1I25.Z0  DST G_842_$1I35.A0 ;
  NET G_842_$1N22  SRC G_842_$1I38.ZN0  DST G_842_$1I25.A1 ;
  NET G_843_Z0  SRC G_843_$1I35.Z0  DST cout1_0.D0 ;
  NET G_843_$1N8  SRC G_843_$1I31.Z0  DST G_843_$1I35.A1 ;
  NET G_843_$1N6  SRC G_843_$1I25.Z0  DST G_843_$1I35.A0 ;
  NET G_843_$1N22  SRC G_843_$1I38.ZN0  DST G_843_$1I25.A1 ;
  NET G_844_Z0  SRC G_844_$1I35.Z0  DST cout1_2.D0 ;
  NET G_844_$1N8  SRC G_844_$1I31.Z0  DST G_844_$1I35.A1 ;
  NET G_844_$1N6  SRC G_844_$1I25.Z0  DST G_844_$1I35.A0 ;
  NET G_844_$1N22  SRC G_844_$1I38.ZN0  DST G_844_$1I25.A1 ;
  NET G_845_Z0  SRC G_845_$1I35.Z0  DST cout2_0.D0 ;
  NET G_845_$1N8  SRC G_845_$1I31.Z0  DST G_845_$1I35.A1 ;
  NET G_845_$1N6  SRC G_845_$1I25.Z0  DST G_845_$1I35.A0 ;
  NET G_845_$1N22  SRC G_845_$1I38.ZN0  DST G_845_$1I25.A1 ;
  NET G_846_Z0  SRC G_846_$1I35.Z0  DST cout2_2.D0 ;
  NET G_846_$1N8  SRC G_846_$1I31.Z0  DST G_846_$1I35.A1 ;
  NET G_846_$1N6  SRC G_846_$1I25.Z0  DST G_846_$1I35.A0 ;
  NET G_846_$1N22  SRC G_846_$1I38.ZN0  DST G_846_$1I25.A1 ;
  NET G_847_Z0  SRC G_847_$1I35.Z0  DST cout3_0.D0 ;
  NET G_847_$1N8  SRC G_847_$1I31.Z0  DST G_847_$1I35.A1 ;
  NET G_847_$1N6  SRC G_847_$1I25.Z0  DST G_847_$1I35.A0 ;
  NET G_847_$1N22  SRC G_847_$1I38.ZN0  DST G_847_$1I25.A1 ;
  NET G_848_Z0  SRC G_848_$1I35.Z0  DST cout3_2.D0 ;
  NET G_848_$1N8  SRC G_848_$1I31.Z0  DST G_848_$1I35.A1 ;
  NET G_848_$1N6  SRC G_848_$1I25.Z0  DST G_848_$1I35.A0 ;
  NET G_848_$1N22  SRC G_848_$1I38.ZN0  DST G_848_$1I25.A1 ;
  NET G_849_Z0  SRC G_849_$1I35.Z0  DST cout4_0.D0 ;
  NET G_849_$1N8  SRC G_849_$1I31.Z0  DST G_849_$1I35.A1 ;
  NET G_849_$1N6  SRC G_849_$1I25.Z0  DST G_849_$1I35.A0 ;
  NET G_849_$1N22  SRC G_849_$1I38.ZN0  DST G_849_$1I25.A1 ;
  NET G_850_Z0  SRC G_850_$1I35.Z0  DST cout4_2.D0 ;
  NET G_850_$1N8  SRC G_850_$1I31.Z0  DST G_850_$1I35.A1 ;
  NET G_850_$1N6  SRC G_850_$1I25.Z0  DST G_850_$1I35.A0 ;
  NET G_850_$1N22  SRC G_850_$1I38.ZN0  DST G_850_$1I25.A1 ;
  NET G_851_Z0  SRC G_851_$1I35.Z0  DST cout5_0.D0 ;
  NET G_851_$1N8  SRC G_851_$1I31.Z0  DST G_851_$1I35.A1 ;
  NET G_851_$1N6  SRC G_851_$1I25.Z0  DST G_851_$1I35.A0 ;
  NET G_851_$1N22  SRC G_851_$1I38.ZN0  DST G_851_$1I25.A1 ;
  NET G_852_Z0  SRC G_852_$1I35.Z0  DST cout5_2.D0 ;
  NET G_852_$1N8  SRC G_852_$1I31.Z0  DST G_852_$1I35.A1 ;
  NET G_852_$1N6  SRC G_852_$1I25.Z0  DST G_852_$1I35.A0 ;
  NET G_852_$1N22  SRC G_852_$1I38.ZN0  DST G_852_$1I25.A1 ;
  NET G_853_Z0  SRC G_853_$1I35.Z0  DST cout6_0.D0 ;
  NET G_853_$1N8  SRC G_853_$1I31.Z0  DST G_853_$1I35.A1 ;
  NET G_853_$1N6  SRC G_853_$1I25.Z0  DST G_853_$1I35.A0 ;
  NET G_853_$1N22  SRC G_853_$1I38.ZN0  DST G_853_$1I25.A1 ;
  NET G_854_Z0  SRC G_854_$1I35.Z0  DST cout6_2.D0 ;
  NET G_854_$1N8  SRC G_854_$1I31.Z0  DST G_854_$1I35.A1 ;
  NET G_854_$1N6  SRC G_854_$1I25.Z0  DST G_854_$1I35.A0 ;
  NET G_854_$1N22  SRC G_854_$1I38.ZN0  DST G_854_$1I25.A1 ;
  NET G_828_Z0  SRC G_828_$1I35.Z0  DST un1_cout0_2_i_0_1.A0 ;
  NET G_828_$1N8  SRC G_828_$1I31.Z0  DST G_828_$1I35.A1 ;
  NET G_828_$1N6  SRC G_828_$1I25.Z0  DST G_828_$1I35.A0 ;
  NET G_828_$1N22  SRC G_828_$1I38.ZN0  DST G_828_$1I25.A1 ;
  NET G_829_Z0  SRC G_829_$1I35.Z0  DST un1_cout0_2_i_0_3.A0 ;
  NET G_829_$1N8  SRC G_829_$1I31.Z0  DST G_829_$1I35.A1 ;
  NET G_829_$1N6  SRC G_829_$1I25.Z0  DST G_829_$1I35.A0 ;
  NET G_829_$1N22  SRC G_829_$1I38.ZN0  DST G_829_$1I25.A1 ;
  NET G_830_Z0  SRC G_830_$1I35.Z0  DST un1_cout1_2_i_0_1.A0 ;
  NET G_830_$1N8  SRC G_830_$1I31.Z0  DST G_830_$1I35.A1 ;
  NET G_830_$1N6  SRC G_830_$1I25.Z0  DST G_830_$1I35.A0 ;
  NET G_830_$1N22  SRC G_830_$1I38.ZN0  DST G_830_$1I25.A1 ;
  NET G_831_Z0  SRC G_831_$1I35.Z0  DST un1_cout1_2_i_0_3.A0 ;
  NET G_831_$1N8  SRC G_831_$1I31.Z0  DST G_831_$1I35.A1 ;
  NET G_831_$1N6  SRC G_831_$1I25.Z0  DST G_831_$1I35.A0 ;
  NET G_831_$1N22  SRC G_831_$1I38.ZN0  DST G_831_$1I25.A1 ;
  NET G_832_Z0  SRC G_832_$1I35.Z0  DST un1_cout2_2_i_0_1.A0 ;
  NET G_832_$1N8  SRC G_832_$1I31.Z0  DST G_832_$1I35.A1 ;
  NET G_832_$1N6  SRC G_832_$1I25.Z0  DST G_832_$1I35.A0 ;
  NET G_832_$1N22  SRC G_832_$1I38.ZN0  DST G_832_$1I25.A1 ;
  NET G_833_Z0  SRC G_833_$1I35.Z0  DST un1_cout2_2_i_0_3.A0 ;
  NET G_833_$1N8  SRC G_833_$1I31.Z0  DST G_833_$1I35.A1 ;
  NET G_833_$1N6  SRC G_833_$1I25.Z0  DST G_833_$1I35.A0 ;
  NET G_833_$1N22  SRC G_833_$1I38.ZN0  DST G_833_$1I25.A1 ;
  NET G_834_Z0  SRC G_834_$1I35.Z0  DST un1_cout3_2_i_0_1.A0 ;
  NET G_834_$1N8  SRC G_834_$1I31.Z0  DST G_834_$1I35.A1 ;
  NET G_834_$1N6  SRC G_834_$1I25.Z0  DST G_834_$1I35.A0 ;
  NET G_834_$1N22  SRC G_834_$1I38.ZN0  DST G_834_$1I25.A1 ;
  NET G_835_Z0  SRC G_835_$1I35.Z0  DST un1_cout3_2_i_0_3.A0 ;
  NET G_835_$1N8  SRC G_835_$1I31.Z0  DST G_835_$1I35.A1 ;
  NET G_835_$1N6  SRC G_835_$1I25.Z0  DST G_835_$1I35.A0 ;
  NET G_835_$1N22  SRC G_835_$1I38.ZN0  DST G_835_$1I25.A1 ;
  NET G_836_Z0  SRC G_836_$1I35.Z0  DST un1_cout4_2_i_0_1.A0 ;
  NET G_836_$1N8  SRC G_836_$1I31.Z0  DST G_836_$1I35.A1 ;
  NET G_836_$1N6  SRC G_836_$1I25.Z0  DST G_836_$1I35.A0 ;
  NET G_836_$1N22  SRC G_836_$1I38.ZN0  DST G_836_$1I25.A1 ;
  NET G_837_Z0  SRC G_837_$1I35.Z0  DST un1_cout5_2_i_0_1.A0 ;
  NET G_837_$1N8  SRC G_837_$1I31.Z0  DST G_837_$1I35.A1 ;
  NET G_837_$1N6  SRC G_837_$1I25.Z0  DST G_837_$1I35.A0 ;
  NET G_837_$1N22  SRC G_837_$1I38.ZN0  DST G_837_$1I25.A1 ;
  NET G_838_Z0  SRC G_838_$1I35.Z0  DST un1_cout5_2_i_0_3.A0 ;
  NET G_838_$1N8  SRC G_838_$1I31.Z0  DST G_838_$1I35.A1 ;
  NET G_838_$1N6  SRC G_838_$1I25.Z0  DST G_838_$1I35.A0 ;
  NET G_838_$1N22  SRC G_838_$1I38.ZN0  DST G_838_$1I25.A1 ;
  NET G_839_Z0  SRC G_839_$1I35.Z0  DST un1_cout6_2_i_0_1.A0 ;
  NET G_839_$1N8  SRC G_839_$1I31.Z0  DST G_839_$1I35.A1 ;
  NET G_839_$1N6  SRC G_839_$1I25.Z0  DST G_839_$1I35.A0 ;
  NET G_839_$1N22  SRC G_839_$1I38.ZN0  DST G_839_$1I25.A1 ;
 SYM FD11 count_2  ;
   PIN Q0 OUT COUNTZ0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN COUNT_3_2;
 END;
 SYM FD11 count3_3  ;
   PIN Q0 OUT COUNT3Z0Z_3;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_874_Z0;
 END;
 SYM FD11 count4_0  ;
   PIN Q0 OUT COUNT4Z0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_868_Z0;
 END;
 SYM FD11 count4_1  ;
   PIN Q0 OUT COUNT4Z0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_869_Z0;
 END;
 SYM FD11 count4_2  ;
   PIN Q0 OUT COUNT4Z0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_870_Z0;
 END;
 SYM FD11 count4_3  ;
   PIN Q0 OUT COUNT4Z0Z_3;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_883_Z0;
 END;
 SYM FD11 count5_0  ;
   PIN Q0 OUT COUNT5Z0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_864_Z0;
 END;
 SYM FD11 count5_1  ;
   PIN Q0 OUT COUNT5Z0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_865_Z0;
 END;
 SYM FD11 count5_2  ;
   PIN Q0 OUT COUNT5Z0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_866_Z0;
 END;
 SYM FD11 count5_3  ;
   PIN Q0 OUT COUNT5Z0Z_3;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_867_Z0;
 END;
 SYM FD11 count6_0  ;
   PIN Q0 OUT COUNT6Z0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_860_Z0;
 END;
 SYM FD11 count6_1  ;
   PIN Q0 OUT COUNT6Z0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_861_Z0;
 END;
 SYM FD11 count6_2  ;
   PIN Q0 OUT COUNT6Z0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_862_Z0;
 END;
 SYM FD11 count6_3  ;
   PIN Q0 OUT COUNT6Z0Z_3;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_863_Z0;
 END;
 SYM FD11 count_0  ;
   PIN Q0 OUT COUNTZ0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN UN4_COUNT_3;
 END;
 SYM FD11 count_1  ;
   PIN Q0 OUT COUNTZ0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN COUNT_3_1;
 END;
 SYM FD11 count0_0  ;
   PIN Q0 OUT COUNT0Z0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_856_Z0;
 END;
 SYM FD11 count0_1  ;
   PIN Q0 OUT COUNT0Z0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_857_Z0;
 END;
 SYM FD11 count0_2  ;
   PIN Q0 OUT COUNT0Z0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_858_Z0;
 END;
 SYM FD11 count0_3  ;
   PIN Q0 OUT COUNT0Z0Z_3;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_859_Z0;
 END;
 SYM FD11 count1_0  ;
   PIN Q0 OUT COUNT1Z0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_879_Z0;
 END;
 SYM FD11 count1_1  ;
   PIN Q0 OUT COUNT1Z0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_880_Z0;
 END;
 SYM FD11 count1_2  ;
   PIN Q0 OUT COUNT1Z0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_881_Z0;
 END;
 SYM FD11 count1_3  ;
   PIN Q0 OUT COUNT1Z0Z_3;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_882_Z0;
 END;
 SYM FD11 count2_0  ;
   PIN Q0 OUT COUNT2Z0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_875_Z0;
 END;
 SYM FD11 count2_1  ;
   PIN Q0 OUT COUNT2Z0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_876_Z0;
 END;
 SYM FD11 count2_2  ;
   PIN Q0 OUT COUNT2Z0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_877_Z0;
 END;
 SYM FD11 count2_3  ;
   PIN Q0 OUT COUNT2Z0Z_3;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_878_Z0;
 END;
 SYM FD11 count3_0  ;
   PIN Q0 OUT COUNT3Z0Z_0;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_871_Z0;
 END;
 SYM FD11 count3_1  ;
   PIN Q0 OUT COUNT3Z0Z_1;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_872_Z0;
 END;
 SYM FD11 count3_2  ;
   PIN Q0 OUT COUNT3Z0Z_2;
   PIN CLK IN clkZ0_Z0;
   PIN D0 IN G_873_Z0;
 END;
 SYM FD21 cout3_1  ;
   PIN Q0 OUT COUT3Z0Z_1;
   PIN CD IN P7_UN10_COUTA;
   PIN CLK IN M2_IZ0;
   PIN D0 IN N_316_I_0;