frequent.ldb

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

DESIGN FREQUENT
{
    PORT data(0) output 
    {
        ATTR LOCK string 1
8

        {

        }

    }
    PORT data(1) output 
    {
        ATTR LOCK string 2
10

        {

        }

    }
    PORT data(2) output 
    {
        ATTR LOCK string 1
5

        {

        }

    }
    PORT data(3) output 
    {
        ATTR LOCK string 1
6

        {

        }

    }
    PORT data(4) output 
    {
        ATTR LOCK string 1
9

        {

        }

    }
    PORT data(5) output 
    {
        ATTR LOCK string 1
7

        {

        }

    }
    PORT data(6) output 
    {
        ATTR LOCK string 1
4

        {

        }

    }
    PORT data(7) output 
    {
        ATTR LOCK string 1
3

        {

        }

    }
    PORT choice(0) output 
    {
        ATTR LOCK string 2
82

        {

        }

    }
    PORT choice(1) output 
    {
        ATTR LOCK string 2
81

        {

        }

    }
    PORT choice(2) output 
    {
        ATTR LOCK string 2
80

        {

        }

    }
    PORT choice(3) output 
    {
        ATTR LOCK string 2
79

        {

        }

    }
    PORT choice(4) output 
    {
        ATTR LOCK string 2
78

        {

        }

    }
    PORT choice(5) output 
    {
        ATTR LOCK string 2
83

        {

        }

    }
    PORT xclk input 
    {
        ATTR LOCK string 2
60

        {

        }

    }
    PORT clk input 
    {
        ATTR LOCK string 2
20

        {

        }

    }
    PORT clk1 input 
    {
        ATTR LOCK string 2
59

        {

        }

    }
    ATTR DESIGN_REV string 3
0.0

    {

    }
    ATTR DESIGN string 8
FREQUENT

    {

    }
    ATTR STAT string 32
edif2laf 1.0 2.6.2001 15.12.15 1

    {

    }
    ATTR TECHNOLOGY string 4
pLSI

    {

    }
    ATTR PART string 18
ispLSI1032E-70LJ84

    {

    }
    ATTR CONFIGURATION string 13
CONFIG_HOLDER

    {
        ATTR $default string 1562
CFG_LST=$default
	VERSION=1.00
	OPTION=
	DEVICE=ispLSI1032E-70LJ84
	RESERVED_PINS=
	TIMING_ANALYSIS=0
	TA_MIN_DELAY=1
	TA_LSPATHS=1
	TA_MAX_PATHS=10
	TA_DEST_NODES=0
	TA_CLK_FREQ=ON
	TA_SETUP_HOLD=ON
	TA_CLK_TO_OUT=ON
	TA_TPD=ON
	TA_ENUM_PATHS=1
	TIMING_FILE=
	PARAMETER_FILE=
	USE_PARAMETER_FILE=OFF
	PERFORM_TA=ON
	PIN_FILE=
	PART_NAME=
	OUTPUT_FORM=
	EXTENDED_ROUTE=ON
	IGNORE_FIXED_PIN=OFF
	USE_GLOBAL_RESET=ON
	EXTENDED_LOGIC_OPT=OFF
	MIN_GLB=1
	CARRY_PIN_DIR=OFF
	CASE_SENSITIVE=OFF
	IGNORE_RESERVE_PIN=OFF
	SECURITY=ON
	ISP=OFF
	ISP_EXCEPT_Y2=OFF
	Y1_AS_RESET=OFF
	PULLUP=ON
	SLOWSLEW=OFF
	OPENDRAIN=OFF
	PORT_LST
		choice(0)	D=OUT	L=82	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		choice(1)	D=OUT	L=81	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		choice(2)	D=OUT	L=80	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		choice(3)	D=OUT	L=79	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		choice(4)	D=OUT	L=78	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		choice(5)	D=OUT	L=83	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		clk	D=IN	L=20	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		clk1	D=IN	L=59	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(0)	D=OUT	L=8	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(1)	D=OUT	L=10	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(2)	D=OUT	L=5	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(3)	D=OUT	L=6	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(4)	D=OUT	L=9	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(5)	D=OUT	L=7	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(6)	D=OUT	L=4	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		data(7)	D=OUT	L=3	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		xclk	D=IN	L=60	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
	PORT_END

	OPTION_LST
		EFFORT=2
		STRATEGY=d
		MAX_GLB_IN=16
		MAX_GLB_OUT=4
	OPTION_END
CFG_END


        {

        }

    }
    ATTR MAX_GLB_IN int 4 16
    {

    }
    ATTR MAX_GLB_OUT int 4 4
    {

    }
    ATTR TOE_AS_IO bool 4 0
    {

    }
    ATTR LOWPOWER bool 4 0
    {

    }
    ATTR OUTDELAY bool 4 0
    {

    }
    ATTR VOLTAGE string 5
VCCIO

    {

    }
    ATTR SECURITY bool 4 1
    {

    }
    ATTR ISP bool 4 0
    {

    }
    ATTR ISP_EXCEPT_Y2 bool 4 0
    {

    }
    ATTR Y1_AS_RESET bool 4 0
    {

    }
    ATTR BSCAN_EXCEPT_Y2 bool 4 0
    {

    }
    ATTR Y0_AS_EXCEPT bool 4 0
    {

    }

}