frequent.lo-

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

ispEXPERT Compiler Release 8.2.010.50, Nov  9 2000 13:09:01

Copyright (C) 1994-2000 by Lattice Semiconductor Corporation.
All Rights Reserved.


Design Process Management 

Renaming existing log file to frequent.lo-
Renaming existing rpt file to frequent.rp-

Preprocessing design 'frequent'...

Processing design 'frequent'...


Logical LAF Reading and Translation 
  
Reading file 'frequent.laf'... 
  
Checking design rules... 
Selected part is 'ispLSI1032E-70LJ84' 
  
Reading hardmacro 'E:\ISPTOOLS\ISPCOMP\macro\ld41'... 
  
Writing output files... 
  
Logical LAF reading and translation completed successfully 


Synthesis and Partitioning 
  
Reading design 'frequent'... 
  
Optimizing logic... 
  
Trying to move PT reset signal to global reset pin... 
      PT reset signal cannot be moved to global reset pin 
      In order to move PT reset signal to global reset pin, the 
      following conditions need to be satisfied: 
      1. There exists at least one pin which drives all register's reset
      signals 
      2. This pin is unlocked 
      3. This pin does not drive any data signals 
      4. This pin can be disjointly decomposed with other pins, if any, 
      which drive reset signals 
  
Partitioning logic into 16-input, 16-input with DIs, functions to 
      minimize delay... 
  
Extracting LXOR2 gates to minimize delay... 
  
Packing functions into GLBs using 16 inputs and 4 outputs per GLB to 
      minimize delay... 
  
Synthesis and partitioning statistics: 
  
Number of Macrocells is 102 
Number of GLBs is 30 
Number of product terms is 369 
Maximum number of GLB levels is 2 
Average number of inputs per GLB is 10.1 
Average number of outputs per GLB is 3.4 
Average number of product terms per GLB is 12.3 
  
Synthesis and partitioning completed successfully 


Physical LAF Reading and Translation

Reading design 'frequent'...

Writing output files...

Physical LAF reading and translation completed successfully


Placement and Routing

Reading design 'frequent'...

Routing
.


Writing output files...

Placement and routing completed successfully


Technology Remapping 
  
Reading design 'frequent'... 
  
Remapping... 
  
Writing output files... 
  
Technology remapping completed successfully 


Physical LAF Reading and Translation

Reading design 'frequent'...

Writing output files...

Physical LAF reading and translation completed successfully


Fusemap Generation

Reading design 'frequent'...

Writing output files...

Fusemap generation completed successfully


Simulation LAF Netlist Generation

Reading design 'frequent'...

Writing output files...


Information: Global reset (XRESET) is generated to reset all registers



Simulation LAF netlist generation completed successfully


Timing Analyzer 
Reading design frequent .... 

43121 WARNING: Design has combinational cycles

Evaluating maximum operating frequency...
Evaluating setup and hold times...
43006 WARNING: No chip input pins drive data input and clock input of any register

Calculating  Tpd Path delays ...

Calculating  Tco Path delays ...

................................................................................................................................................................              


Timing analyzer completed successfully 
Node Observability Analyzer Software Version 8.2.010.50.00, Aug 17 2000 
      03:22:20 
  
Copyright (C) 1999-2000 by Lattice Semiconductor Corporation. 
All Rights Reserved. 
  
Reading design 'frequent'... 
  
Writing output files... 
  
Node Observability Analyzer completed successfully 


Design process management completed successfully