frequent.vhm

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

    ZN0 => COUNT6_I_0(1),
    A0 => COUNT6(1));
  \II_COUNT2_I[1]\: INV port map (
    ZN0 => COUNT2_I_0(1),
    A0 => COUNT2(1));
  \II_COUNT3_I[1]\: INV port map (
    ZN0 => COUNT3_I_0(1),
    A0 => COUNT3(1));
  \II_COUNT4_I[1]\: INV port map (
    ZN0 => COUNT4_I_0(1),
    A0 => COUNT4(1));
  \II_COUNT5_I[1]\: INV port map (
    ZN0 => COUNT5_I_0(1),
    A0 => COUNT5(1));
  \II_COUT0_I[1]\: INV port map (
    ZN0 => COUT0_I(1),
    A0 => COUT0(1));
  \II_COUT0_I[2]\: INV port map (
    ZN0 => COUT0_I(2),
    A0 => COUT0(2));
  \II_COUT1_I[1]\: INV port map (
    ZN0 => COUT1_I(1),
    A0 => COUT1(1));
  \II_COUT1_I[2]\: INV port map (
    ZN0 => COUT1_I(2),
    A0 => COUT1(2));
  II_UN1_M3_1_I_MUX2_0_MUX2: MUX2 port map (
    Z0 => N_909,
    A0 => M3_I,
    A1 => N_1098,
    S0 => COUTA(3));
  II_UN1_M4_1_I_MUX2_0_MUX2: MUX2 port map (
    Z0 => N_910,
    A0 => M4_I,
    A1 => N_1097,
    S0 => COUTA(3));
  II_UN1_M5_1_I_MUX2_0_MUX2: MUX2 port map (
    Z0 => N_911,
    A0 => M5_I,
    A1 => N_1096,
    S0 => COUTA(3));
  II_N_209_I: INV port map (
    ZN0 => N_209_I_0_C,
    A0 => N_209);
  II_M5_I: INV port map (
    ZN0 => M5_I,
    A0 => M5);
  II_M4_I: INV port map (
    ZN0 => M4_I,
    A0 => M4);
  II_M3_I: INV port map (
    ZN0 => M3_I,
    A0 => M3);
  II_M2_I: INV port map (
    ZN0 => M2_I,
    A0 => M2);
  II_M1_I: INV port map (
    ZN0 => M1_I,
    A0 => M1);
  II_M0_I: INV port map (
    ZN0 => M0_I,
    A0 => M0);
  \II_COUNT_I[0]\: INV port map (
    ZN0 => COUNT_I(0),
    A0 => COUNT(0));
  \II_COUTA_I[3]\: INV port map (
    ZN0 => COUTA_I(3),
    A0 => COUTA(3));
  \II_COUNT0_I[3]\: INV port map (
    ZN0 => COUNT0_I_0(3),
    A0 => COUNT0(3));
  \II_COUNT1_I[3]\: INV port map (
    ZN0 => COUNT1_I_0(3),
    A0 => COUNT1(3));
  \II_COUNT6_I[3]\: INV port map (
    ZN0 => COUNT6_I_0(3),
    A0 => COUNT6(3));
  \II_UN1_COUT3_2_I_0_AND2[3]\: AND2 port map (
    Z0 => N_943,
    A0 => COUTA(3),
    A1 => N_1098);
  \II_UN1_COUT5_2_I_0_AND2[3]\: AND2 port map (
    Z0 => N_944,
    A0 => COUTA(3),
    A1 => N_1096);
  \II_UN1_COUT6_2_I_0_AND2[3]\: AND2 port map (
    Z0 => N_945,
    A0 => COUTA(3),
    A1 => N_1095);
  II_P7_UN10_COUTA_0_AND2_0_AND2: AND2 port map (
    Z0 => P7_UN10_COUTA,
    A0 => COUTA_I(3),
    A1 => N_638_I_0);
  \II_UN1_COUT4_2_I_0_AND2[3]\: AND2 port map (
    Z0 => N_947,
    A0 => COUTA(3),
    A1 => N_1097);
  II_UN18_COUNT6_0_AND2_0_AND2: AND2 port map (
    Z0 => N_948,
    A0 => COUNT(0),
    A1 => COUNT(1));
  II_UN13_COUNT6_0_AND2_0_AND2: AND2 port map (
    Z0 => N_949,
    A0 => COUNT_I(0),
    A1 => COUNT(1));
  II_UN23_COUNT6_0_AND2_0_AND2: AND2 port map (
    Z0 => N_950,
    A0 => COUNT_I(0),
    A1 => COUNT(2));
  II_UN6_COUNT6_0_AND2_0_AND2_0_AND2: AND2 port map (
    Z0 => N_951,
    A0 => COUNT_I(0),
    A1 => N_960);
  II_UN8_COUNT6_0_AND2_0_AND2_0_AND2: AND2 port map (
    Z0 => N_952,
    A0 => COUNT(0),
    A1 => N_960);
  \II_COUNT_3_0_AND2_0_AND2[2]\: AND2 port map (
    Z0 => COUNT_3(2),
    A0 => UN1_COUNT,
    A1 => UN4_COUNT(1));
  \II_COUNT_3_0_AND2_0_AND2[1]\: AND2 port map (
    Z0 => COUNT_3(1),
    A0 => UN1_COUNT,
    A1 => UN4_COUNT(2));
  II_UN1_M0_1_I_MUX2_0_MUX2: MUX2 port map (
    Z0 => N_906,
    A0 => M0_I,
    A1 => N_1101,
    S0 => COUTA(3));
  II_UN1_M1_1_I_MUX2_0_MUX2: MUX2 port map (
    Z0 => N_907,
    A0 => M1_I,
    A1 => N_1100,
    S0 => COUTA(3));
  II_UN1_M2_1_I_MUX2_0_MUX2: MUX2 port map (
    Z0 => N_908,
    A0 => M2_I,
    A1 => N_1099,
    S0 => COUTA(3));
  \II_TEMP_11_0_0_AND2_1[1]\: AND2 port map (
    Z0 => N_928,
    A0 => COUNT3_I_0(1),
    A1 => N_963);
  \II_TEMP_11_0_0_AND2_2[1]\: AND2 port map (
    Z0 => N_929,
    A0 => COUNT2_I_0(1),
    A1 => N_967);
  \II_TEMP_11_0_0_AND2_3[1]\: AND2 port map (
    Z0 => N_930,
    A0 => COUNT6_I_0(1),
    A1 => N_962);
  \II_TEMP_11_0_0_AND2_4[1]\: AND2 port map (
    Z0 => N_931,
    A0 => COUNT1_I_0(1),
    A1 => N_965);
  \II_TEMP_11_0_0_AND2_5[1]\: AND2 port map (
    Z0 => N_932,
    A0 => COUNT0_I_0(1),
    A1 => N_964);
  \II_TEMP_11_0_0_AND2[3]\: AND2 port map (
    Z0 => N_933,
    A0 => COUNT5_I_0(3),
    A1 => N_819);
  \II_TEMP_11_0_0_AND2_0[3]\: AND2 port map (
    Z0 => N_934,
    A0 => COUNT4_I_0(3),
    A1 => N_966);
  \II_TEMP_11_0_0_AND2_1[3]\: AND2 port map (
    Z0 => N_935,
    A0 => COUNT3_I_0(3),
    A1 => N_963);
  \II_TEMP_11_0_0_AND2_2[3]\: AND2 port map (
    Z0 => N_936,
    A0 => COUNT2_I_0(3),
    A1 => N_967);
  \II_TEMP_11_0_0_AND2_3[3]\: AND2 port map (
    Z0 => N_937,
    A0 => COUNT6_I_0(3),
    A1 => N_962);
  \II_TEMP_11_0_0_AND2_4[3]\: AND2 port map (
    Z0 => N_938,
    A0 => COUNT1_I_0(3),
    A1 => N_965);
  \II_TEMP_11_0_0_AND2_5[3]\: AND2 port map (
    Z0 => N_939,
    A0 => COUNT0_I_0(3),
    A1 => N_964);
  \II_UN1_COUT0_2_I_0_AND2[3]\: AND2 port map (
    Z0 => N_940,
    A0 => COUTA(3),
    A1 => N_1101);
  \II_UN1_COUT1_2_I_0_AND2[3]\: AND2 port map (
    Z0 => N_941,
    A0 => COUTA(3),
    A1 => N_1100);
  \II_UN1_COUT2_2_I_0_AND2[3]\: AND2 port map (
    Z0 => N_942,
    A0 => COUTA(3),
    A1 => N_1099);
  \II_TEMP_11_0_0_AND2_0[0]\: AND2 port map (
    Z0 => N_913,
    A0 => COUNT4(0),
    A1 => N_966);
  \II_TEMP_11_0_0_AND2_1[0]\: AND2 port map (
    Z0 => N_914,
    A0 => COUNT3(0),
    A1 => N_963);
  \II_TEMP_11_0_0_AND2_2[0]\: AND2 port map (
    Z0 => N_915,
    A0 => COUNT2(0),
    A1 => N_967);
  \II_TEMP_11_0_0_AND2_3[0]\: AND2 port map (
    Z0 => N_916,
    A0 => COUNT6(0),
    A1 => N_962);
  \II_TEMP_11_0_0_AND2_4[0]\: AND2 port map (
    Z0 => N_917,
    A0 => COUNT1(0),
    A1 => N_965);
  \II_TEMP_11_0_0_AND2_5[0]\: AND2 port map (
    Z0 => N_918,
    A0 => COUNT0(0),
    A1 => N_964);
  \II_TEMP_11_0_0_AND2[2]\: AND2 port map (
    Z0 => N_919,
    A0 => COUNT5(2),
    A1 => N_819);
  \II_TEMP_11_0_0_AND2_0[2]\: AND2 port map (
    Z0 => N_920,
    A0 => COUNT4(2),
    A1 => N_966);
  \II_TEMP_11_0_0_AND2_1[2]\: AND2 port map (
    Z0 => N_921,
    A0 => COUNT3(2),
    A1 => N_963);
  \II_TEMP_11_0_0_AND2_2[2]\: AND2 port map (
    Z0 => N_922,
    A0 => COUNT2(2),
    A1 => N_967);
  \II_TEMP_11_0_0_AND2_3[2]\: AND2 port map (
    Z0 => N_923,
    A0 => COUNT6(2),
    A1 => N_962);
  \II_TEMP_11_0_0_AND2_4[2]\: AND2 port map (
    Z0 => N_924,
    A0 => COUNT1(2),
    A1 => N_965);
  \II_TEMP_11_0_0_AND2_5[2]\: AND2 port map (
    Z0 => N_925,
    A0 => COUNT0(2),
    A1 => N_964);
  \II_TEMP_11_0_0_AND2[1]\: AND2 port map (
    Z0 => N_926,
    A0 => COUNT5_I_0(1),
    A1 => N_819);
  \II_TEMP_11_0_0_AND2_0[1]\: AND2 port map (
    Z0 => N_927,
    A0 => COUNT4_I_0(1),
    A1 => N_966);
  II_G_870: MUX2 port map (
    Z0 => N_871,
    A0 => COUT4(2),
    A1 => COUNT4(2),
    S0 => N_816);
  II_G_871: MUX2 port map (
    Z0 => N_872,
    A0 => COUT3(0),
    A1 => COUNT3(0),
    S0 => N_816);
  II_G_872: MUX2 port map (
    Z0 => N_873,
    A0 => COUT3(1),
    A1 => COUNT3(1),
    S0 => N_816);
  II_G_873: MUX2 port map (
    Z0 => N_874,
    A0 => COUT3(2),
    A1 => COUNT3(2),
    S0 => N_816);
  II_G_874: MUX2 port map (
    Z0 => N_875,
    A0 => COUT3(3),
    A1 => COUNT3(3),
    S0 => N_816);
  II_G_875: MUX2 port map (
    Z0 => N_876,
    A0 => COUT2(0),
    A1 => COUNT2(0),
    S0 => N_816);
  II_G_876: MUX2 port map (
    Z0 => N_877,
    A0 => COUT2(1),
    A1 => COUNT2(1),
    S0 => N_816);
  II_G_877: MUX2 port map (
    Z0 => N_878,
    A0 => COUT2(2),
    A1 => COUNT2(2),
    S0 => N_816);
  II_G_878: MUX2 port map (
    Z0 => N_879,
    A0 => COUT2(3),
    A1 => COUNT2(3),
    S0 => N_816);
  II_G_879: MUX2 port map (
    Z0 => N_880,
    A0 => COUT1(0),
    A1 => COUNT1(0),
    S0 => N_816);
  II_G_880: MUX2 port map (
    Z0 => N_881,
    A0 => COUT1(1),
    A1 => COUNT1(1),
    S0 => N_816);
  II_G_881: MUX2 port map (
    Z0 => N_882,
    A0 => COUT1(2),
    A1 => COUNT1(2),
    S0 => N_816);
  II_G_882: MUX2 port map (
    Z0 => N_883,
    A0 => COUT1(3),
    A1 => COUNT1(3),
    S0 => N_816);
  II_G_883: MUX2 port map (
    Z0 => N_884,
    A0 => COUT4(3),
    A1 => COUNT4(3),
    S0 => N_816);
  \II_TEMP_11_0_0_AND2[0]\: AND2 port map (
    Z0 => N_912,
    A0 => COUNT5(0),
    A1 => N_819);
  II_G_855: MUX2 port map (
    Z0 => N_856,
    A0 => COUT4(3),
    A1 => UN5_COUT4(1),
    S0 => COUTA(3));
  II_G_856: MUX2 port map (
    Z0 => N_857,
    A0 => COUT0(0),
    A1 => COUNT0(0),
    S0 => N_816);
  II_G_857: MUX2 port map (
    Z0 => N_858,
    A0 => COUT0(1),
    A1 => COUNT0(1),
    S0 => N_816);
  II_G_858: MUX2 port map (
    Z0 => N_859,
    A0 => COUT0(2),
    A1 => COUNT0(2),
    S0 => N_816);
  II_G_859: MUX2 port map (
    Z0 => N_860,
    A0 => COUT0(3),
    A1 => COUNT0(3),
    S0 => N_816);
  II_G_860: MUX2 port map (
    Z0 => N_861,
    A0 => COUT6(0),
    A1 => COUNT6(0),
    S0 => N_816);
  II_G_861: MUX2 port map (
    Z0 => N_862,
    A0 => COUT6(1),
    A1 => COUNT6(1),
    S0 => N_816);
  II_G_862: MUX2 port map (
    Z0 => N_863,
    A0 => COUT6(2),
    A1 => COUNT6(2),
    S0 => N_816);
  II_G_863: MUX2 port map (
    Z0 => N_864,
    A0 => COUT6(3),
    A1 => COUNT6(3),
    S0 => N_816);
  II_G_864: MUX2 port map (
    Z0 => N_865,
    A0 => COUT5(0),
    A1 => COUNT5(0),
    S0 => N_816);
  II_G_865: MUX2 port map (
    Z0 => N_866,
    A0 => COUT5(1),
    A1 => COUNT5(1),
    S0 => N_816);
  II_G_866: MUX2 port map (
    Z0 => N_867,
    A0 => COUT5(2),
    A1 => COUNT5(2),
    S0 => N_816);
  II_G_867: MUX2 port map (
    Z0 => N_868,
    A0 => COUT5(3),
    A1 => COUNT5(3),
    S0 => N_816);
  II_G_868: MUX2 port map (
    Z0 => N_869,
    A0 => COUT4(0),
    A1 => COUNT4(0),
    S0 => N_816);
  II_G_869: MUX2 port map (
    Z0 => N_870,
    A0 => COUT4(1),
    A1 => COUNT4(1),
    S0 => N_816);
  II_G_840: MUX2 port map (
    Z0 => N_841,
    A0 => COUT6(3),
    A1 => UN5_COUT6(1),
    S0 => COUTA(3));
  II_G_841: MUX2 port map (
    Z0 => N_842,
    A0 => COUT0(0),
    A1 => UN5_COUT0(4),
    S0 => COUTA(3));
  II_G_842: MUX2 port map (
    Z0 => N_843,
    A0 => COUT0(2),
    A1 => UN5_COUT0(2),
    S0 => COUTA(3));
  II_G_843: MUX2 port map (
    Z0 => N_844,
    A0 => COUT1(0),
    A1 => UN5_COUT1(4),
    S0 => COUTA(3));
  II_G_844: MUX2 port map (
    Z0 => N_845,
    A0 => COUT1(2),
    A1 => UN5_COUT1(2),
    S0 => COUTA(3));
  II_G_845: MUX2 port map (
    Z0 => N_846,
    A0 => COUT2(0),
    A1 => UN5_COUT2(4),
    S0 => COUTA(3));
  II_G_846: MUX2 port map (
    Z0 => N_847,
    A0 => COUT2(2),
    A1 => UN5_COUT2(2),
    S0 => COUTA(3));
  II_G_847: MUX2 port map (
    Z0 => N_848,
    A0 => COUT3(0),
    A1 => UN5_COUT3(4),
    S0 => COUTA(3));
  II_G_848: MUX2 port map (
    Z0 => N_849,
    A0 => COUT3(2),
    A1 => UN5_COUT3(2),
    S0 => COUTA(3));
  II_G_849: MUX2 port map (
    Z0 => N_850,
    A0 => COUT4(0),
    A1 => UN5_COUT4(4),
    S0 => COUTA(3));
  II_G_850: MUX2 port map (
    Z0 => N_851,
    A0 => COUT4(2),
    A1 => UN5_COUT4(2),
    S0 => COUTA(3));
  II_G_851: MUX2 port map (
    Z0 => N_852,
    A0 => COUT5(0),
    A1 => UN5_COUT5(4),
    S0 => COUTA(3));
  II_G_852: MUX2 port map (
    Z0 => N_853,
    A0 => COUT5(2),
    A1 => UN5_COUT5(2),
    S0 => COUTA(3));
  II_G_853: MUX2 port map (
    Z0 => N_854,
    A0 => COUT6(0),
    A1 => UN5_COUT6(4),
    S0 => COUTA(3));
  II_G_854: MUX2 port map (
    Z0 => N_855,
    A0 => COUT6(2),
    A1 => UN5_COUT6(2),
    S0 => COUTA(3));
  II_G_816: AND2 port map (
    Z0 => N_1134,
    A0 => N_955_I,
    A1 => N_956_I);
  II_G_817: AND2 port map (
    Z0 => N_1133,
    A0 => N_968_I,
    A1 => N_957_I);
  II_G_818: AND2 port map (
    Z0 => N_1132,
    A0 => N_958_I,
    A1 => N_959_I);
  II_G_828: MUX2 port map (
    Z0 => N_829,
    A0 => COUT0(1),
    A1 => UN5_COUT0(3),
    S0 => COUTA(3));
  II_G_829: MUX2 port map (
    Z0 => N_830,
    A0 => COUT0(3),
    A1 => UN5_COUT0(1),
    S0 => COUTA(3));
  II_G_830: MUX2 port map (
    Z0 => N_831,
    A0 => COUT1(1),
    A1 => UN5_COUT1(3),
    S0 => COUTA(3));
  II_G_831: MUX2 port map (
    Z0 => N_832,
    A0 => COUT1(3),
    A1 => UN5_COUT1(1),
    S0 => COUTA(3));
  II_G_832: MUX2 port map (
    Z0 => N_833,
    A0 => COUT2(1),
    A1 => UN5_COUT2(3),
    S0 => COUTA(3));
  II_G_833: MUX2 port map (
    Z0 => N_834,
    A0 => COUT2(3),
    A1 => UN5_COUT2(1),
    S0 => COUTA(3));
  II_G_834: MUX2 port map (
    Z0 => N_835,
    A0 => COUT3(1),
    A1 => UN5_COUT3(3),
    S0 => COUTA(