📄 frequent.vhm
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\II_CHOICE[2]\: OB11 port map (
XO0 => choice(2),
A0 => CHOICE_1_C(2));
\II_CHOICE[3]\: OB11 port map (
XO0 => choice(3),
A0 => CHOICE_1_C(3));
\II_CHOICE[4]\: OB11 port map (
XO0 => choice(4),
A0 => CHOICE_1_C(4));
\II_CHOICE[5]\: OB11 port map (
XO0 => choice(5),
A0 => CHOICE_1_C(5));
\II_TEMP_11_0_0_2.G_987\: AND2 port map (
Z0 => N_1238,
A0 => N_1235,
A1 => N_922_I);
\II_TEMP_11_0_0_2.G_988\: AND2 port map (
Z0 => N_1239,
A0 => N_921_I,
A1 => N_1238);
\II_TEMP_11_0_0_0.G_972\: AND2 port map (
Z0 => N_1223,
A0 => N_1220,
A1 => N_915_I);
\II_TEMP_11_0_0_0.G_973\: AND2 port map (
Z0 => N_1224,
A0 => N_914_I,
A1 => N_1223);
\II_TEMP_11_0_0_1.G_974\: AND2 port map (
Z0 => N_1225,
A0 => N_930_I,
A1 => N_932_I);
\II_TEMP_11_0_0_1.G_975\: AND2 port map (
Z0 => N_1226,
A0 => N_927_I,
A1 => N_931_I);
\II_TEMP_11_0_0_1.G_976\: AND2 port map (
Z0 => N_1227,
A0 => N_926_I,
A1 => N_1226);
\II_TEMP_11_0_0_1.G_977\: AND2 port map (
Z0 => N_1228,
A0 => N_1225,
A1 => N_929_I);
\II_TEMP_11_0_0_1.G_978\: AND2 port map (
Z0 => N_1229,
A0 => N_928_I,
A1 => N_1228);
\II_TEMP_11_0_0_3.G_979\: AND2 port map (
Z0 => N_1230,
A0 => N_937_I,
A1 => N_939_I);
\II_TEMP_11_0_0_3.G_980\: AND2 port map (
Z0 => N_1231,
A0 => N_934_I,
A1 => N_938_I);
\II_TEMP_11_0_0_3.G_981\: AND2 port map (
Z0 => N_1232,
A0 => N_933_I,
A1 => N_1231);
\II_TEMP_11_0_0_3.G_982\: AND2 port map (
Z0 => N_1233,
A0 => N_1230,
A1 => N_936_I);
\II_TEMP_11_0_0_3.G_983\: AND2 port map (
Z0 => N_1234,
A0 => N_935_I,
A1 => N_1233);
\II_TEMP_11_0_0_2.G_984\: AND2 port map (
Z0 => N_1235,
A0 => N_923_I,
A1 => N_925_I);
\II_TEMP_11_0_0_2.G_985\: AND2 port map (
Z0 => N_1236,
A0 => N_920_I,
A1 => N_924_I);
\II_TEMP_11_0_0_2.G_986\: AND2 port map (
Z0 => N_1237,
A0 => N_919_I,
A1 => N_1236);
\II_G_804.G_957\: AND2 port map (
Z0 => N_1208,
A0 => COUT4_I(1),
A1 => COUT4(0));
\II_G_804.G_958\: AND2 port map (
Z0 => N_1209,
A0 => COUT4(3),
A1 => COUT4_I(2));
\II_G_803.G_959\: AND2 port map (
Z0 => N_1210,
A0 => COUT5_I(2),
A1 => COUT5(3));
\II_G_803.G_960\: AND2 port map (
Z0 => N_1211,
A0 => COUT5(0),
A1 => COUT5_I(1));
\II_G_802.G_961\: AND2 port map (
Z0 => N_1212,
A0 => COUT6_I(2),
A1 => COUT6_I(1));
\II_G_802.G_962\: AND2 port map (
Z0 => N_1213,
A0 => COUT6(3),
A1 => COUT6(0));
\II_G_806.G_963\: AND2 port map (
Z0 => N_1214,
A0 => COUT2_I(2),
A1 => COUT2(3));
\II_G_806.G_964\: AND2 port map (
Z0 => N_1215,
A0 => COUT2(0),
A1 => COUT2_I(1));
\II_DATA_1_I_0_3.G_965\: AND2 port map (
Z0 => N_1216,
A0 => TEMP_I_0(0),
A1 => DATA_1_C_I(0));
\II_G_171.G_966\: AND2 port map (
Z0 => N_1217,
A0 => TEMP_I_0(1),
A1 => TEMP_I_0(3));
\II_G_171.G_967\: AND2 port map (
Z0 => N_1218,
A0 => N_1217,
A1 => N_211_I);
\II_DATA_1_I_0_6.G_968\: AND2 port map (
Z0 => N_1219,
A0 => DATA_1_C_I(0),
A1 => N_207_I);
\II_TEMP_11_0_0_0.G_969\: AND2 port map (
Z0 => N_1220,
A0 => N_916_I,
A1 => N_918_I);
\II_TEMP_11_0_0_0.G_970\: AND2 port map (
Z0 => N_1221,
A0 => N_913_I,
A1 => N_917_I);
\II_TEMP_11_0_0_0.G_971\: AND2 port map (
Z0 => N_1222,
A0 => N_912_I,
A1 => N_1221);
II_G_808: AND2 port map (
Z0 => N_1101,
A0 => N_1201,
A1 => N_1202);
\II_TEMP_11_0_0[3]\: AND2 port map (
Z0 => TEMP_11_IV_I(3),
A0 => N_1232,
A1 => N_1234);
\II_TEMP_11_0_0[1]\: AND2 port map (
Z0 => TEMP_11_IV_I(1),
A0 => N_1227,
A1 => N_1229);
\II_TEMP_11_0_0[2]\: AND2 port map (
Z0 => N_1114,
A0 => N_1237,
A1 => N_1239);
\II_TEMP_11_0_0[0]\: AND2 port map (
Z0 => N_1108,
A0 => N_1222,
A1 => N_1224);
\II_DATA_1_I_0_AND2[6]\: AND2 port map (
Z0 => N_207,
A0 => TEMP(1),
A1 => N_1205);
\II_DATA_1_I_0[6]\: AND2 port map (
Z0 => N_33_I_C,
A0 => N_208_I,
A1 => N_1219);
\II_DATA_1_I_0[3]\: AND2 port map (
Z0 => N_27_I_C,
A0 => N_213_I,
A1 => N_1216);
\II_G_808.G_950\: AND2 port map (
Z0 => N_1201,
A0 => COUT0_I(2),
A1 => COUT0(3));
\II_G_808.G_951\: AND2 port map (
Z0 => N_1202,
A0 => COUT0(0),
A1 => COUT0_I(1));
\II_G_807.G_952\: AND2 port map (
Z0 => N_1203,
A0 => COUT1_I(2),
A1 => COUT1(3));
\II_G_807.G_953\: AND2 port map (
Z0 => N_1204,
A0 => COUT1(0),
A1 => COUT1_I(1));
\II_DATA_1_I_0_AND2_6.G_954\: AND2 port map (
Z0 => N_1205,
A0 => TEMP(2),
A1 => TEMP_I_0(0));
\II_G_805.G_955\: AND2 port map (
Z0 => N_1206,
A0 => COUT3_I(2),
A1 => COUT3(3));
\II_G_805.G_956\: AND2 port map (
Z0 => N_1207,
A0 => COUT3(0),
A1 => COUT3_I(1));
II_N_207_I: INV port map (
ZN0 => N_207_I,
A0 => N_207);
II_N_208_I: INV port map (
ZN0 => N_208_I,
A0 => N_208);
II_N_206_I: INV port map (
ZN0 => N_206_I,
A0 => N_206);
II_N_213_I: INV port map (
ZN0 => N_213_I,
A0 => N_213);
II_N_203_I: INV port map (
ZN0 => N_203_I,
A0 => N_203);
II_N_204_I: INV port map (
ZN0 => N_204_I,
A0 => N_204);
II_N_201_I: INV port map (
ZN0 => N_201_I,
A0 => N_201);
II_N_202_I: INV port map (
ZN0 => N_202_I,
A0 => N_202);
II_G_171: AND2 port map (
Z0 => N_210,
A0 => N_212_I,
A1 => N_1218);
II_G_802: AND2 port map (
Z0 => N_1095,
A0 => N_1212,
A1 => N_1213);
II_G_803: AND2 port map (
Z0 => N_1096,
A0 => N_1210,
A1 => N_1211);
II_G_804: AND2 port map (
Z0 => N_1097,
A0 => N_1208,
A1 => N_1209);
II_G_805: AND2 port map (
Z0 => N_1098,
A0 => N_1206,
A1 => N_1207);
II_G_806: AND2 port map (
Z0 => N_1099,
A0 => N_1214,
A1 => N_1215);
II_G_807: AND2 port map (
Z0 => N_1100,
A0 => N_1203,
A1 => N_1204);
II_N_943_I: INV port map (
ZN0 => N_943_I,
A0 => N_943);
II_N_1098_I: INV port map (
ZN0 => N_1098_I,
A0 => N_1098);
II_N_942_I: INV port map (
ZN0 => N_942_I,
A0 => N_942);
II_N_1099_I: INV port map (
ZN0 => N_1099_I,
A0 => N_1099);
II_N_941_I: INV port map (
ZN0 => N_941_I,
A0 => N_941);
II_N_1100_I: INV port map (
ZN0 => N_1100_I,
A0 => N_1100);
II_N_940_I: INV port map (
ZN0 => N_940_I,
A0 => N_940);
II_N_1101_I: INV port map (
ZN0 => N_1101_I,
A0 => N_1101);
II_G_548_I: INV port map (
ZN0 => N_638,
A0 => N_638_I_0);
II_N_210_I: INV port map (
ZN0 => N_210_I,
A0 => N_210);
\II_DATA_1_C_I[0]\: INV port map (
ZN0 => DATA_1_C_I(0),
A0 => DATA_1_C(0));
II_G_184_I: INV port map (
ZN0 => N_198,
A0 => N_1153);
II_N_211_I: INV port map (
ZN0 => N_211_I,
A0 => N_211);
II_G_183_I: INV port map (
ZN0 => N_197,
A0 => N_1154);
II_N_212_I: INV port map (
ZN0 => N_212_I,
A0 => N_212);
II_N_959_I: INV port map (
ZN0 => N_959_I,
A0 => N_959);
II_G_818_I: INV port map (
ZN0 => N_819,
A0 => N_1132);
II_N_968_I: INV port map (
ZN0 => N_968_I,
A0 => N_968);
II_N_957_I: INV port map (
ZN0 => N_957_I,
A0 => N_957);
II_G_817_I: INV port map (
ZN0 => N_818,
A0 => N_1133);
II_N_955_I: INV port map (
ZN0 => N_955_I,
A0 => N_955);
II_N_956_I: INV port map (
ZN0 => N_956_I,
A0 => N_956);
II_G_816_I: INV port map (
ZN0 => N_817,
A0 => N_1134);
II_G_815_I: INV port map (
ZN0 => N_816,
A0 => N_1135);
II_N_947_I: INV port map (
ZN0 => N_947_I,
A0 => N_947);
II_N_945_I: INV port map (
ZN0 => N_945_I,
A0 => N_945);
II_N_1095_I: INV port map (
ZN0 => N_1095_I,
A0 => N_1095);
II_N_944_I: INV port map (
ZN0 => N_944_I,
A0 => N_944);
II_N_1096_I: INV port map (
ZN0 => N_1096_I,
A0 => N_1096);
II_N_1097_I: INV port map (
ZN0 => N_1097_I,
A0 => N_1097);
II_N_932_I: INV port map (
ZN0 => N_932_I,
A0 => N_932);
II_N_930_I: INV port map (
ZN0 => N_930_I,
A0 => N_930);
II_N_931_I: INV port map (
ZN0 => N_931_I,
A0 => N_931);
II_N_928_I: INV port map (
ZN0 => N_928_I,
A0 => N_928);
II_N_929_I: INV port map (
ZN0 => N_929_I,
A0 => N_929);
II_N_926_I: INV port map (
ZN0 => N_926_I,
A0 => N_926);
II_N_927_I: INV port map (
ZN0 => N_927_I,
A0 => N_927);
II_N_939_I: INV port map (
ZN0 => N_939_I,
A0 => N_939);
II_N_937_I: INV port map (
ZN0 => N_937_I,
A0 => N_937);
II_N_938_I: INV port map (
ZN0 => N_938_I,
A0 => N_938);
II_N_935_I: INV port map (
ZN0 => N_935_I,
A0 => N_935);
II_N_936_I: INV port map (
ZN0 => N_936_I,
A0 => N_936);
II_N_933_I: INV port map (
ZN0 => N_933_I,
A0 => N_933);
II_N_934_I: INV port map (
ZN0 => N_934_I,
A0 => N_934);
II_N_958_I: INV port map (
ZN0 => N_958_I,
A0 => N_958);
II_N_918_I: INV port map (
ZN0 => N_918_I,
A0 => N_918);
II_N_916_I: INV port map (
ZN0 => N_916_I,
A0 => N_916);
II_N_917_I: INV port map (
ZN0 => N_917_I,
A0 => N_917);
II_N_914_I: INV port map (
ZN0 => N_914_I,
A0 => N_914);
II_N_915_I: INV port map (
ZN0 => N_915_I,
A0 => N_915);
II_N_912_I: INV port map (
ZN0 => N_912_I,
A0 => N_912);
II_N_913_I: INV port map (
ZN0 => N_913_I,
A0 => N_913);
\II_TEMP_11_0_0_I[2]\: INV port map (
ZN0 => TEMP_11(2),
A0 => N_1114);
II_N_925_I: INV port map (
ZN0 => N_925_I,
A0 => N_925);
II_N_923_I: INV port map (
ZN0 => N_923_I,
A0 => N_923);
II_N_924_I: INV port map (
ZN0 => N_924_I,
A0 => N_924);
II_N_921_I: INV port map (
ZN0 => N_921_I,
A0 => N_921);
II_N_922_I: INV port map (
ZN0 => N_922_I,
A0 => N_922);
II_N_919_I: INV port map (
ZN0 => N_919_I,
A0 => N_919);
II_N_920_I: INV port map (
ZN0 => N_920_I,
A0 => N_920);
\II_TEMP_11_0_0_I[0]\: INV port map (
ZN0 => TEMP_11(0),
A0 => N_1108);
\II_TEMP_I[0]\: INV port map (
ZN0 => TEMP_I_0(0),
A0 => TEMP(0));
\II_TEMP_I[1]\: INV port map (
ZN0 => TEMP_I_0(1),
A0 => TEMP(1));
\II_TEMP_I[2]\: INV port map (
ZN0 => TEMP_I_0(2),
A0 => TEMP(2));
\II_TEMP_I[3]\: INV port map (
ZN0 => TEMP_I_0(3),
A0 => TEMP(3));
\II_COUNT6_I[0]\: INV port map (
ZN0 => COUNT6_I_0(0),
A0 => COUNT6(0));
\II_COUNT6_I[2]\: INV port map (
ZN0 => COUNT6_I_0(2),
A0 => COUNT6(2));
II_N_911_I: INV port map (
ZN0 => N_911_I,
A0 => N_911);
II_N_910_I: INV port map (
ZN0 => N_910_I,
A0 => N_910);
II_N_909_I: INV port map (
ZN0 => N_909_I,
A0 => N_909);
II_N_908_I: INV port map (
ZN0 => N_908_I,
A0 => N_908);
II_N_907_I: INV port map (
ZN0 => N_907_I,
A0 => N_907);
II_N_906_I: INV port map (
ZN0 => N_906_I,
A0 => N_906);
\II_COUT2_I[1]\: INV port map (
ZN0 => COUT2_I(1),
A0 => COUT2(1));
\II_COUT2_I[2]\: INV port map (
ZN0 => COUT2_I(2),
A0 => COUT2(2));
\II_COUT3_I[1]\: INV port map (
ZN0 => COUT3_I(1),
A0 => COUT3(1));
\II_COUT3_I[2]\: INV port map (
ZN0 => COUT3_I(2),
A0 => COUT3(2));
\II_COUT4_I[2]\: INV port map (
ZN0 => COUT4_I(2),
A0 => COUT4(2));
\II_COUT4_I[1]\: INV port map (
ZN0 => COUT4_I(1),
A0 => COUT4(1));
\II_COUT5_I[1]\: INV port map (
ZN0 => COUT5_I(1),
A0 => COUT5(1));
\II_COUT5_I[2]\: INV port map (
ZN0 => COUT5_I(2),
A0 => COUT5(2));
\II_COUT6_I[2]\: INV port map (
ZN0 => COUT6_I(2),
A0 => COUT6(2));
\II_COUT6_I[1]\: INV port map (
ZN0 => COUT6_I(1),
A0 => COUT6(1));
II_UN4_COUNT6_I: INV port map (
ZN0 => UN4_COUNT6_I,
A0 => UN4_COUNT6);
II_UN1_COUNT_I: INV port map (
ZN0 => UN1_COUNT_I,
A0 => UN1_COUNT);
\II_COUNT_I[2]\: INV port map (
ZN0 => COUNT_I(2),
A0 => COUNT(2));
\II_COUNT_I[1]\: INV port map (
ZN0 => COUNT_I(1),
A0 => COUNT(1));
\II_COUTA_I[0]\: INV port map (
ZN0 => COUTA_I(0),
A0 => COUTA(0));
\II_COUNT2_I[3]\: INV port map (
ZN0 => COUNT2_I_0(3),
A0 => COUNT2(3));
\II_COUNT3_I[3]\: INV port map (
ZN0 => COUNT3_I_0(3),
A0 => COUNT3(3));
\II_COUNT4_I[3]\: INV port map (
ZN0 => COUNT4_I_0(3),
A0 => COUNT4(3));
\II_COUNT5_I[3]\: INV port map (
ZN0 => COUNT5_I_0(3),
A0 => COUNT5(3));
\II_COUNT0_I[1]\: INV port map (
ZN0 => COUNT0_I_0(1),
A0 => COUNT0(1));
\II_COUNT1_I[1]\: INV port map (
ZN0 => COUNT1_I_0(1),
A0 => COUNT1(1));
\II_COUNT6_I[1]\: INV port map (
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