📄 frequent.vhm
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\II_COUT3[3]\: FD21 port map (
Q0 => COUT3(3),
D0 => N_320_I_0,
CLK => M2_I,
CD => P7_UN10_COUTA);
\II_COUT4[0]\: FD21 port map (
Q0 => COUT4(0),
D0 => N_850,
CLK => M3_I,
CD => P7_UN10_COUTA);
\II_COUT4[1]\: FD21 port map (
Q0 => COUT4(1),
D0 => N_324_I_0,
CLK => M3_I,
CD => P7_UN10_COUTA);
\II_COUT4[2]\: FD21 port map (
Q0 => COUT4(2),
D0 => N_851,
CLK => M3_I,
CD => P7_UN10_COUTA);
\II_COUT4[3]\: FD21 port map (
Q0 => COUT4(3),
D0 => N_616_I_0,
CLK => M3_I,
CD => P7_UN10_COUTA);
\II_COUT5[0]\: FD21 port map (
Q0 => COUT5(0),
D0 => N_852,
CLK => M4_I,
CD => P7_UN10_COUTA);
\II_COUT5[1]\: FD21 port map (
Q0 => COUT5(1),
D0 => N_330_I_0,
CLK => M4_I,
CD => P7_UN10_COUTA);
\II_COUT5[2]\: FD21 port map (
Q0 => COUT5(2),
D0 => N_853,
CLK => M4_I,
CD => P7_UN10_COUTA);
\II_COUT5[3]\: FD21 port map (
Q0 => COUT5(3),
D0 => N_334_I_0,
CLK => M4_I,
CD => P7_UN10_COUTA);
\II_COUT6[0]\: FD21 port map (
Q0 => COUT6(0),
D0 => N_854,
CLK => M5_I,
CD => P7_UN10_COUTA);
\II_COUT6[1]\: FD21 port map (
Q0 => COUT6(1),
D0 => N_338_I_0,
CLK => M5_I,
CD => P7_UN10_COUTA);
\II_COUT6[2]\: FD21 port map (
Q0 => COUT6(2),
D0 => N_855,
CLK => M5_I,
CD => P7_UN10_COUTA);
\II_COUT6[3]\: FD21 port map (
Q0 => COUT6(3),
D0 => N_342_I_0,
CLK => M5_I,
CD => P7_UN10_COUTA);
\II_COUT0[0]\: FD21 port map (
Q0 => COUT0(0),
D0 => N_842,
CLK => XCLK_C,
CD => P7_UN10_COUTA);
\II_COUT0[1]\: FD21 port map (
Q0 => COUT0(1),
D0 => N_292_I_0,
CLK => XCLK_C,
CD => P7_UN10_COUTA);
\II_COUT0[2]\: FD21 port map (
Q0 => COUT0(2),
D0 => N_843,
CLK => XCLK_C,
CD => P7_UN10_COUTA);
\II_COUT0[3]\: FD21 port map (
Q0 => COUT0(3),
D0 => N_296_I_0,
CLK => XCLK_C,
CD => P7_UN10_COUTA);
\II_COUT1[0]\: FD21 port map (
Q0 => COUT1(0),
D0 => N_844,
CLK => M0_I,
CD => P7_UN10_COUTA);
\II_COUT1[1]\: FD21 port map (
Q0 => COUT1(1),
D0 => N_300_I_0,
CLK => M0_I,
CD => P7_UN10_COUTA);
\II_COUT1[2]\: FD21 port map (
Q0 => COUT1(2),
D0 => N_845,
CLK => M0_I,
CD => P7_UN10_COUTA);
\II_COUT1[3]\: FD21 port map (
Q0 => COUT1(3),
D0 => N_304_I_0,
CLK => M0_I,
CD => P7_UN10_COUTA);
\II_COUT2[0]\: FD21 port map (
Q0 => COUT2(0),
D0 => N_846,
CLK => M1_I,
CD => P7_UN10_COUTA);
\II_COUT2[1]\: FD21 port map (
Q0 => COUT2(1),
D0 => N_308_I_0,
CLK => M1_I,
CD => P7_UN10_COUTA);
\II_COUT2[2]\: FD21 port map (
Q0 => COUT2(2),
D0 => N_847,
CLK => M1_I,
CD => P7_UN10_COUTA);
\II_COUT2[3]\: FD21 port map (
Q0 => COUT2(3),
D0 => N_312_I_0,
CLK => M1_I,
CD => P7_UN10_COUTA);
\II_COUT3[0]\: FD21 port map (
Q0 => COUT3(0),
D0 => N_848,
CLK => M2_I,
CD => P7_UN10_COUTA);
\II_TEMP[0]\: FD11 port map (
Q0 => TEMP(0),
D0 => TEMP_11(0),
CLK => CLK_C);
\II_TEMP[1]\: FD11 port map (
Q0 => TEMP(1),
D0 => TEMP_11_IV_I(1),
CLK => CLK_C);
\II_TEMP[2]\: FD11 port map (
Q0 => TEMP(2),
D0 => TEMP_11(2),
CLK => CLK_C);
\II_TEMP[3]\: FD11 port map (
Q0 => TEMP(3),
D0 => TEMP_11_IV_I(3),
CLK => CLK_C);
\II_COUTA[0]\: FD11 port map (
Q0 => COUTA(0),
D0 => COUTA_I(0),
CLK => CLK1_C);
\II_COUTA[1]\: FD11 port map (
Q0 => COUTA(1),
D0 => COUTA_N1,
CLK => CLK1_C);
\II_COUTA[2]\: FD11 port map (
Q0 => COUTA(2),
D0 => COUTA_N2,
CLK => CLK1_C);
\II_COUTA[3]\: FD11 port map (
Q0 => COUTA(3),
D0 => COUTA_N3,
CLK => CLK1_C);
II_M0: FD21 port map (
Q0 => M0,
D0 => N_906_I,
CLK => XCLK_C,
CD => P7_UN10_COUTA);
II_M1: FD21 port map (
Q0 => M1,
D0 => N_907_I,
CLK => M0_I,
CD => P7_UN10_COUTA);
II_M2: FD21 port map (
Q0 => M2,
D0 => N_908_I,
CLK => M1_I,
CD => P7_UN10_COUTA);
II_M3: FD21 port map (
Q0 => M3,
D0 => N_909_I,
CLK => M2_I,
CD => P7_UN10_COUTA);
II_M4: FD21 port map (
Q0 => M4,
D0 => N_910_I,
CLK => M3_I,
CD => P7_UN10_COUTA);
II_M5: FD21 port map (
Q0 => M5,
D0 => N_911_I,
CLK => M4_I,
CD => P7_UN10_COUTA);
II_I_45: XOR2 port map (
Z0 => UN4_COUNT(3),
A0 => COUNT(0),
A1 => VCC);
II_I_46: AND2 port map (
Z0 => N_61,
A0 => COUNT(0),
A1 => VCC);
II_I_47: XOR2 port map (
Z0 => UN4_COUNT(2),
A0 => COUNT(1),
A1 => N_61);
II_I_48: AND2 port map (
Z0 => N_65,
A0 => COUNT(1),
A1 => N_61);
II_I_49: XOR2 port map (
Z0 => UN4_COUNT(1),
A0 => COUNT(2),
A1 => N_65);
II_I_54: AND2 port map (
Z0 => N_69,
A0 => COUNT6_I_0(3),
A1 => GND);
II_I_55: OR2 port map (
Z0 => N_70,
A0 => COUNT6_I_0(3),
A1 => GND);
II_I_56: AND2 port map (
Z0 => N_71,
A0 => COUNT6_I_0(2),
A1 => GND);
II_I_57: OR2 port map (
Z0 => N_72,
A0 => COUNT6_I_0(2),
A1 => GND);
II_I_58: AND2 port map (
Z0 => N_73,
A0 => COUNT6_I_0(1),
A1 => GND);
II_I_59: OR2 port map (
Z0 => N_74,
A0 => COUNT6_I_0(1),
A1 => GND);
II_I_60: AND2 port map (
Z0 => N_75,
A0 => COUNT6_I_0(0),
A1 => VCC);
II_I_61: AND2 port map (
Z0 => N_76,
A0 => N_74,
A1 => N_75);
II_I_62: OR2 port map (
Z0 => N_77,
A0 => N_73,
A1 => N_76);
II_I_63: AND2 port map (
Z0 => N_78,
A0 => N_72,
A1 => N_77);
II_I_64: OR2 port map (
Z0 => N_79,
A0 => N_71,
A1 => N_78);
II_I_65: AND2 port map (
Z0 => N_80,
A0 => N_70,
A1 => N_79);
II_I_66: OR2 port map (
Z0 => UN4_COUNT6,
A0 => N_69,
A1 => N_80);
II_I_67: XOR2 port map (
Z0 => UN5_COUT0(4),
A0 => COUT0(0),
A1 => VCC);
II_I_68: AND2 port map (
Z0 => N_84,
A0 => COUT0(0),
A1 => VCC);
II_I_69: XOR2 port map (
Z0 => UN5_COUT0(3),
A0 => COUT0(1),
A1 => N_84);
II_I_70: AND2 port map (
Z0 => N_88,
A0 => COUT0(1),
A1 => N_84);
II_I_71: XOR2 port map (
Z0 => UN5_COUT0(2),
A0 => COUT0(2),
A1 => N_88);
II_I_72: AND2 port map (
Z0 => N_91,
A0 => COUT0(2),
A1 => N_88);
II_I_73: XOR2 port map (
Z0 => UN5_COUT0(1),
A0 => COUT0(3),
A1 => N_91);
II_I_79: XOR2 port map (
Z0 => UN5_COUT1(4),
A0 => COUT1(0),
A1 => VCC);
II_I_80: AND2 port map (
Z0 => N_97,
A0 => COUT1(0),
A1 => VCC);
II_I_81: XOR2 port map (
Z0 => UN5_COUT1(3),
A0 => COUT1(1),
A1 => N_97);
II_I_82: AND2 port map (
Z0 => N_101,
A0 => COUT1(1),
A1 => N_97);
II_I_83: XOR2 port map (
Z0 => UN5_COUT1(2),
A0 => COUT1(2),
A1 => N_101);
II_I_84: AND2 port map (
Z0 => N_104,
A0 => COUT1(2),
A1 => N_101);
II_I_85: XOR2 port map (
Z0 => UN5_COUT1(1),
A0 => COUT1(3),
A1 => N_104);
II_I_91: XOR2 port map (
Z0 => UN5_COUT2(4),
A0 => COUT2(0),
A1 => VCC);
II_I_92: AND2 port map (
Z0 => N_110,
A0 => COUT2(0),
A1 => VCC);
II_I_93: XOR2 port map (
Z0 => UN5_COUT2(3),
A0 => COUT2(1),
A1 => N_110);
II_I_94: AND2 port map (
Z0 => N_114,
A0 => COUT2(1),
A1 => N_110);
II_I_95: XOR2 port map (
Z0 => UN5_COUT2(2),
A0 => COUT2(2),
A1 => N_114);
II_I_96: AND2 port map (
Z0 => N_117,
A0 => COUT2(2),
A1 => N_114);
II_I_97: XOR2 port map (
Z0 => UN5_COUT2(1),
A0 => COUT2(3),
A1 => N_117);
II_I_103: XOR2 port map (
Z0 => UN5_COUT3(4),
A0 => COUT3(0),
A1 => VCC);
II_I_104: AND2 port map (
Z0 => N_123,
A0 => COUT3(0),
A1 => VCC);
II_I_105: XOR2 port map (
Z0 => UN5_COUT3(3),
A0 => COUT3(1),
A1 => N_123);
II_I_106: AND2 port map (
Z0 => N_127,
A0 => COUT3(1),
A1 => N_123);
II_I_107: XOR2 port map (
Z0 => UN5_COUT3(2),
A0 => COUT3(2),
A1 => N_127);
II_I_108: AND2 port map (
Z0 => N_130,
A0 => COUT3(2),
A1 => N_127);
II_I_109: XOR2 port map (
Z0 => UN5_COUT3(1),
A0 => COUT3(3),
A1 => N_130);
II_I_115: XOR2 port map (
Z0 => UN5_COUT4(4),
A0 => COUT4(0),
A1 => VCC);
II_I_116: AND2 port map (
Z0 => N_136,
A0 => COUT4(0),
A1 => VCC);
II_I_117: XOR2 port map (
Z0 => UN5_COUT4(3),
A0 => COUT4(1),
A1 => N_136);
II_I_118: AND2 port map (
Z0 => N_140,
A0 => COUT4(1),
A1 => N_136);
II_I_119: XOR2 port map (
Z0 => UN5_COUT4(2),
A0 => COUT4(2),
A1 => N_140);
II_I_120: AND2 port map (
Z0 => N_143,
A0 => COUT4(2),
A1 => N_140);
II_I_121: XOR2 port map (
Z0 => UN5_COUT4(1),
A0 => COUT4(3),
A1 => N_143);
II_I_127: XOR2 port map (
Z0 => UN5_COUT5(4),
A0 => COUT5(0),
A1 => VCC);
II_I_128: AND2 port map (
Z0 => N_149,
A0 => COUT5(0),
A1 => VCC);
II_I_129: XOR2 port map (
Z0 => UN5_COUT5(3),
A0 => COUT5(1),
A1 => N_149);
II_I_130: AND2 port map (
Z0 => N_153,
A0 => COUT5(1),
A1 => N_149);
II_I_131: XOR2 port map (
Z0 => UN5_COUT5(2),
A0 => COUT5(2),
A1 => N_153);
II_I_132: AND2 port map (
Z0 => N_156,
A0 => COUT5(2),
A1 => N_153);
II_I_133: XOR2 port map (
Z0 => UN5_COUT5(1),
A0 => COUT5(3),
A1 => N_156);
II_I_139: XOR2 port map (
Z0 => UN5_COUT6(4),
A0 => COUT6(0),
A1 => VCC);
II_I_140: AND2 port map (
Z0 => N_162,
A0 => COUT6(0),
A1 => VCC);
II_I_141: XOR2 port map (
Z0 => UN5_COUT6(3),
A0 => COUT6(1),
A1 => N_162);
II_I_142: AND2 port map (
Z0 => N_166,
A0 => COUT6(1),
A1 => N_162);
II_I_143: XOR2 port map (
Z0 => UN5_COUT6(2),
A0 => COUT6(2),
A1 => N_166);
II_I_144: AND2 port map (
Z0 => N_169,
A0 => COUT6(2),
A1 => N_166);
II_I_145: XOR2 port map (
Z0 => UN5_COUT6(1),
A0 => COUT6(3),
A1 => N_169);
II_I_151: AND2 port map (
Z0 => N_173,
A0 => COUNT_I(2),
A1 => VCC);
II_I_152: OR2 port map (
Z0 => N_174,
A0 => COUNT_I(2),
A1 => VCC);
II_I_153: AND2 port map (
Z0 => N_175,
A0 => COUNT_I(1),
A1 => GND);
II_I_154: OR2 port map (
Z0 => N_176,
A0 => COUNT_I(1),
A1 => GND);
II_I_155: AND2 port map (
Z0 => N_177,
A0 => COUNT_I(0),
A1 => VCC);
II_I_156: AND2 port map (
Z0 => N_178,
A0 => N_176,
A1 => N_177);
II_I_157: OR2 port map (
Z0 => N_179,
A0 => N_175,
A1 => N_178);
II_I_158: AND2 port map (
Z0 => N_180,
A0 => N_174,
A1 => N_179);
II_I_159: OR2 port map (
Z0 => UN1_COUNT,
A0 => N_173,
A1 => N_180);
II_XCLK: IB11 port map (
Z0 => XCLK_C,
XI0 => xclk);
II_CLK: IB11 port map (
Z0 => CLK_C,
XI0 => clk);
II_CLK1: IB11 port map (
Z0 => CLK1_C,
XI0 => clk1);
\II_DATA[0]\: OB11 port map (
XO0 => data(0),
A0 => DATA_1_C(0));
\II_DATA[1]\: OB11 port map (
XO0 => data(1),
A0 => N_23_I_C);
\II_DATA[2]\: OB11 port map (
XO0 => data(2),
A0 => N_25_I_C);
\II_DATA[3]\: OB11 port map (
XO0 => data(3),
A0 => N_27_I_C);
\II_DATA[4]\: OB11 port map (
XO0 => data(4),
A0 => N_29_I_C);
\II_DATA[5]\: OB11 port map (
XO0 => data(5),
A0 => N_209_I_0_C);
\II_DATA[6]\: OB11 port map (
XO0 => data(6),
A0 => N_33_I_C);
\II_DATA[7]\: OB11 port map (
XO0 => data(7),
A0 => N_193_I_0_C);
\II_CHOICE[0]\: OB11 port map (
XO0 => choice(0),
A0 => CHOICE_1_C(0));
\II_CHOICE[1]\: OB11 port map (
XO0 => choice(1),
A0 => CHOICE_1_C(1));
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