frequent.vhm

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

--
-- Written by Synplicity
-- Sat Jun 02 15:12:26 2001
--

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XINPUT is
port(
  Z0 :  out std_logic;
  XI0 :  in std_logic);
end XINPUT;

architecture beh of XINPUT is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  Z0 <= XI0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XOUTPUT is
port(
  XO0 :  out std_logic;
  A0 :  in std_logic);
end XOUTPUT;

architecture beh of XOUTPUT is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  XO0 <= A0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFF_FD is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CP :  in std_logic;
  R :  in std_logic);
end DFF_FD;

architecture beh of DFF_FD is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_dff port map (Q, D, CP, R, '0');
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity BUF is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic);
end BUF;

architecture beh of BUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  Z0 <= A0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OR4 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic;
  A2 :  in std_logic;
  A3 :  in std_logic);
end OR4;

architecture beh of OR4 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 or A1 or A2 or A3  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity AND3 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic;
  A2 :  in std_logic);
end AND3;

architecture beh of AND3 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 and A1 and A2  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OR2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end OR2;

architecture beh of OR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 or A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity AND2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 and A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity INV is
port(
  ZN0 :  out std_logic;
  A0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  ZN0 <= not A0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity IB11 is
port(
  Z0 :  out std_logic;
  XI0 :  in std_logic);
end IB11;

architecture beh of IB11 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component XINPUT
    port(Z0 :  out std_logic;
    XI0 :  in std_logic  );
  end component;
begin
  \II_$1I45\: XINPUT port map (
    Z0 => Z0,
    XI0 => XI0);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity LD41 is
port(
  Q0 :  out std_logic;
  D0 :  in std_logic;
  G :  in std_logic;
  PD :  in std_logic;
  CD :  in std_logic);
end LD41;

architecture beh of LD41 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal \$1N288\ : std_logic ;
  signal \$1N188\ : std_logic ;
  signal \$1N293\ : std_logic ;
  signal \$1N159\ : std_logic ;
  signal \$1N166\ : std_logic ;
  signal \$1N6\ : std_logic ;
  signal \$1N223\ : std_logic ;
  component INV
    port(ZN0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
  component AND3
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic;
    A2 :  in std_logic  );
  end component;
  component AND2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic  );
  end component;
  component OR4
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic;
    A2 :  in std_logic;
    A3 :  in std_logic  );
  end component;
  component BUF
    port(Z0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
begin
  \II_$1I226\: INV port map (
    ZN0 => \$1N223\,
    A0 => CD);
  \II_$1I277\: AND3 port map (
    Z0 => \$1N166\,
    A0 => \$1N6\,
    A1 => \$1N223\,
    A2 => D0);
  \II_$1I278\: AND3 port map (
    Z0 => \$1N159\,
    A0 => \$1N6\,
    A1 => \$1N223\,
    A2 => \$1N293\);
  \II_$1I279\: AND3 port map (
    Z0 => \$1N188\,
    A0 => D0,
    A1 => \$1N223\,
    A2 => G);
  \II_$1I284\: AND2 port map (
    Z0 => \$1N288\,
    A0 => \$1N223\,
    A1 => PD);
  \II_$1I287\: OR4 port map (
    Z0 => \$1N6\,
    A0 => \$1N166\,
    A1 => \$1N159\,
    A2 => \$1N188\,
    A3 => \$1N288\);
  \II_$1I292\: INV port map (
    ZN0 => \$1N293\,
    A0 => G);
  \II_$1I314\: BUF port map (
    Z0 => Q0,
    A0 => \$1N6\);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity MUX2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic;
  S0 :  in std_logic);
end MUX2;

architecture beh of MUX2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal \$1N8\ : std_logic ;
  signal \$1N22\ : std_logic ;
  signal \$1N6\ : std_logic ;
  component AND2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic  );
  end component;
  component OR2
    port(Z0 :  out std_logic;
    A0 :  in std_logic;
    A1 :  in std_logic  );
  end component;
  component INV
    port(ZN0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
begin
  \II_$1I25\: AND2 port map (
    Z0 => \$1N6\,
    A0 => A0,
    A1 => \$1N22\);
  \II_$1I31\: AND2 port map (
    Z0 => \$1N8\,
    A0 => A1,
    A1 => S0);
  \II_$1I35\: OR2 port map (
    Z0 => Z0,
    A0 => \$1N6\,
    A1 => \$1N8\);
  \II_$1I38\: INV port map (
    ZN0 => \$1N22\,
    A0 => S0);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OB11 is
port(
  XO0 :  out std_logic;
  A0 :  in std_logic);
end OB11;

architecture beh of OB11 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component XOUTPUT
    port(XO0 :  out std_logic;
    A0 :  in std_logic  );
  end component;
begin
  \II_$1I42\: XOUTPUT port map (
    XO0 => XO0,
    A0 => A0);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity FD11 is
port(
  Q0 :  out std_logic;
  D0 :  in std_logic;
  CLK :  in std_logic);
end FD11;

architecture beh of FD11 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component DFF_FD
    port(Q :  out std_logic;
    D :  in std_logic;
    CP :  in std_logic;
    R :  in std_logic  );
  end component;
begin
  II_BLK2: DFF_FD port map (
    Q => Q0,
    D => D0,
    CP => CLK,
    R => NN_1);
  NN_2 <= '1';
  NN_1 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity FD21 is
port(
  Q0 :  out std_logic;
  D0 :  in std_logic;
  CLK :  in std_logic;
  CD :  in std_logic);
end FD21;

architecture beh of FD21 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component DFF_FD
    port(Q :  out std_logic;
    D :  in std_logic;
    CP :  in std_logic;
    R :  in std_logic  );
  end component;
begin
  II_BLK2: DFF_FD port map (
    Q => Q0,
    D => D0,
    CP => CLK,
    R => CD);
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XOR2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end XOR2;

architecture beh of XOR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  Z0 <= A0 xor A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity frequent is
port(
  xclk :  in std_logic;
  clk :  in std_logic;
  clk1 :  in std_logic;
  data : out std_logic_vector(7 downto 0);
  choice : out std_logic_vector(5 downto 0));
end frequent;

architecture beh of frequent is
  signal COUTA : std_logic_vector(3 downto 0);
  signal COUT0 : std_logic_vector(3 downto 0);
  signal COUT1 : std_logic_vector(3 downto 0);
  signal COUT2 : std_logic_vector(3 downto 0);
  signal COUT3 : std_logic_vector(3 downto 0);
  signal COUT4 : std_logic_vector(3 downto 0);
  signal COUT5 : std_logic_vector(3 downto 0);
  signal COUT6 : std_logic_vector(3 downto 0);
  signal COUNT : std_logic_vector(2 downto 0);
  signal TEMP : std_logic_vector(3 downto 0);
  signal UN4_COUNT : std_logic_vector(3 downto 1);
  signal COUNT6 : std_logic_vector(3 downto 0);
  signal UN5_COUT0 : std_logic_vector(4 downto 1);
  signal UN5_COUT1 : std_logic_vector(4 downto 1);
  signal UN5_COUT2 : std_logic_vector(4 downto 1);
  signal UN5_COUT3 : std_logic_vector(4 downto 1);
  signal UN5_COUT4 : std_logic_vector(4 downto 1);
  signal UN5_COUT5 : std_logic_vector(4 downto 1);
  signal UN5_COUT6 : std_logic_vector(4 downto 1);
  signal COUNT0 : std_logic_vector(3 downto 0);
  signal COUNT5 : std_logic_vector(3 downto 0);
  signal COUNT4 : std_logic_vector(3 downto 0);
  signal COUNT3 : std_logic_vector(3 downto 0);
  signal COUNT2 : std_logic_vector(3 downto 0);
  signal COUNT1 : std_logic_vector(3 downto 0);
  signal TEMP_11 : std_logic_vector(2 downto 0);
  signal COUNT_3 : std_logic_vector(2 downto 1);
  signal COUNT_I : std_logic_vector(2 downto 0);
  signal COUTA_I : std_logic_vector(3 downto 0);
  signal COUNT0_I_0 : std_logic_vector(3 downto 1);
  signal COUNT1_I_0 : std_logic_vector(3 downto 1);
  signal COUNT6_I_0 : std_logic_vector(3 downto 0);
  signal COUNT2_I_0 : std_logic_vector(3 downto 1);
  signal COUNT3_I_0 : std_logic_vector(3 downto 1);
  signal COUNT4_I_0 : std_logic_vector(3 downto 1);
  signal COUNT5_I_0 : std_logic_vector(3 downto 1);
  signal COUT0_I : std_logic_vector(2 downto 1);
  signal COUT1_I : std_logic_vector(2 downto 1);
  signal COUT2_I : std_logic_vector(2 downto 1);
  signal COUT3_I : std_logic_vector(2 downto 1);
  signal COUT4_I : std_logic_vector(2 downto 1);
  signal COUT5_I : std_logic_vector(2 downto 1);
  signal COUT6_I : std_logic_vector(2 downto 1);
  signal TEMP_I_0 : std_logic_vector(3 downto 0);
  signal DATA_1_C : std_logic_vector(0 to 0);
  signal CHOICE_1_C : std_logic_vector(5 downto 0);
  signal DATA_1_C_I : std_logic_vector(0 to 0);
  signal TEMP_11_IV_I : std_logic_vector(3 downto 1);