frequent.tc_

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

#-- Synplicity, Inc.
#-- Synplify version 5.3.2
#-- Project file C:\My Documents\shudianku\frequent\frequent.tc_
#-- Written on Sat Jun 02 15:12:14 2001

#device options
set_option -technology pLSI

#add_file options
add_file -vhdl -lib work "frequent.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
set_option -resource_sharing true

#map options
set_option -frequency 0.000
set_option -top_module frequent

#simulation options
set_option -write_verilog true
set_option -write_vhdl true

#automatic place and route (vendor) options
set_option -write_apr_constraint true

#MTI Cross Probe options
set_option -mti_root ""

#set result format/file last
project -result_file "frequent.edn"