frequent.rpt

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

ispEXPERT Compiler Release 8.2.010.50, Nov  9 2000 13:09:01


Design Parameters
-----------------

EFFORT:                         MEDIUM (2)
IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16
MAX_GLB_OUT:                    4
OS_VERSION:                     Windows 98
PARAM_FILE:                     '_frequen'
PIN_FILE:                       'frequent.xpn'
STRATEGY:                       DELAY
TIMING_ANALYZER:                FREQUENCY SETUP_HOLD CLOCK_TO_OUTPUT PRIMARY_IN_TO_OUT 
USE_GLOBAL_RESET:               ON
XOR:                            OFF


Design Specification
--------------------

Design:                         frequent
Part:                           ispLSI1032E-70LJ84


ISP:                            OFF
PULL:                           UP
SECURITY:                       ON
SLOWSLEW:                       OFF


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          17
Number of Reserved Pins:        0


Input Pins

    Pin Name                Pin Attribute

        CLK                     LOCK 20, PULLUP
        CLK1                    LOCK 59, PULLUP
        XCLK                    LOCK 60, PULLUP


Output Pins

    Pin Name                Pin Attribute

        CHOICE(0)               LOCK 82, PULLUP
        CHOICE(1)               LOCK 81, PULLUP
        CHOICE(2)               LOCK 80, PULLUP
        CHOICE(3)               LOCK 79, PULLUP
        CHOICE(4)               LOCK 78, PULLUP
        CHOICE(5)               LOCK 83, PULLUP
        DATA(0)                 LOCK 8, PULLUP
        DATA(1)                 LOCK 10, PULLUP
        DATA(2)                 LOCK 5, PULLUP
        DATA(3)                 LOCK 6, PULLUP
        DATA(4)                 LOCK 9, PULLUP
        DATA(5)                 LOCK 7, PULLUP
        DATA(6)                 LOCK 4, PULLUP
        DATA(7)                 LOCK 3, PULLUP


Hardmacro Instances

    Instance Name           Hardmacro Name

        CHOICE_1_0              LD41
        CHOICE_1_1              LD41
        CHOICE_1_2              LD41
        CHOICE_1_3              LD41
        CHOICE_1_4              LD41
        CHOICE_1_5              LD41


Pre-Route Design Statistics
---------------------------

Number of Macrocells:           102
Number of GLBs:                 29
Number of I/Os:                 16
Number of Nets:                 102

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    2
Number of Locked DIs:           0
Number of Locked Outputs:       14
Number of Locked Three-States:  0
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      1


GLB Utilization (Out of 32):	90%
I/O Utilization (Out of 72):	22%
Net Utilization (Out of 200):	51%


Nets with Fanout of  1:         19
Nets with Fanout of  2:         55
Nets with Fanout of  3:         16
Nets with Fanout of  4:         3
Nets with Fanout of  5:         2
Nets with Fanout of  6:         3
Nets with Fanout of 21:         4

Average Fanout per Net:         2.95


GLBs with  4 Input(s):          2
GLBs with  5 Input(s):          2
GLBs with  6 Input(s):          3
GLBs with  8 Input(s):          2
GLBs with  9 Input(s):          2
GLBs with 10 Input(s):          4
GLBs with 11 Input(s):          1
GLBs with 12 Input(s):          8
GLBs with 13 Input(s):          1
GLBs with 14 Input(s):          2
GLBs with 15 Input(s):          2

Average Inputs per GLB:         9.93


GLBs with  1 Output(s):         4
GLBs with  3 Output(s):         2
GLBs with  4 Output(s):         23

Average Outputs per GLB:        3.52


Number of GLB Registers:        73
Number of IOC Registers:        0


Post-Route Design Implementation
--------------------------------

Number of Macrocells:		102
Number of GLBs:			29
Number of IOCs:			16
Number of DIs:			0
Number of GLB Levels:		2


GLB glb00, C3

    8 Input(s)
        (glb00.O2, CHOICE_1_C_0, I17), (glb00.O1, CHOICE_1_C_1, I16), 
        (glb00.O0, CHOICE_1_C_2, I7), (glb00.O3, CHOICE_1_C_5, I4), 
        (glb04.O1, N_949, I10), (glb04.O2, N_948, I9), (glb05.O3, 
        N_951, I0), (glb05.O2, N_952, I5)
    4 Output(s)
        (CHOICE_1_C_5, O3), (CHOICE_1_C_2, O0), (CHOICE_1_C_1, O1), 
        (CHOICE_1_C_0, O2)
    8 Product Term(s)

    Output CHOICE_1_C_5

        2 Input(s)
            N_951, CHOICE_1_C_5
        2 Fanout(s)
            glb00.I4, CHOICE(5).IR
        2 Product Term(s)
        2 GLB Level(s)

        CHOICE_1_C_5 = CHOICE_1_C_5 & !N_951
            # !N_951

    Output CHOICE_1_C_2

        2 Input(s)
            N_948, CHOICE_1_C_2
        2 Fanout(s)
            glb00.I7, CHOICE(2).IR
        2 Product Term(s)
        2 GLB Level(s)

        CHOICE_1_C_2 = CHOICE_1_C_2 & !N_948
            # !N_948

    Output CHOICE_1_C_1

        2 Input(s)
            N_949, CHOICE_1_C_1
        2 Fanout(s)
            glb00.I16, CHOICE(1).IR
        2 Product Term(s)
        2 GLB Level(s)

        CHOICE_1_C_1 = CHOICE_1_C_1 & !N_949
            # !N_949

    Output CHOICE_1_C_0

        2 Input(s)
            CHOICE_1_C_0, N_952
        2 Fanout(s)
            glb00.I17, CHOICE(0).IR
        2 Product Term(s)
        2 GLB Level(s)

        CHOICE_1_C_0 = CHOICE_1_C_0 & !N_952
            # !N_952


Clock GLB glb01, C0

    14 Input(s)
        (glb01.O3, CHOICE_1_C_3, I8), (glb01.O2, CHOICE_1_C_4, I17), 
        (glb15.O3, COUT0Z0Z_0, I15), (glb15.O2, COUT0Z0Z_1, I14), 
        (glb15.O1, COUT0Z0Z_2, I13), (glb15.O0, COUT0Z0Z_3, I12), 
        (glb16.O3, COUTAZ0Z_0, I4), (glb16.O2, COUTAZ0Z_1, I5), 
        (glb16.O1, COUTAZ0Z_2, I6), (glb16.O0, COUTAZ0Z_3, I7), 
        (glb01.O0, MZ0Z0, I16), (glb05.O0, UN1_COUNT_IZ0, I3), 
        (glb13.O0, N_950, I11), (XCLK.O, XCLKX, I0)
    4 Output(s)
        (MZ0Z0, O0), (CHOICE_1_C_4, O2), (CHOICE_1_C_3, O3), 
        (BUF_2760, O1)
    8 Product Term(s)

    Output MZ0Z0

        9 Input(s)
            MZ0Z0, COUT0Z0Z_3, COUTAZ0Z_0, COUT0Z0Z_2, COUTAZ0Z_1,
            COUT0Z0Z_1, COUTAZ0Z_2, COUT0Z0Z_0, COUTAZ0Z_3
        3 Fanout(s)
            glb20.CLK1, glb01.I16, glb11.CLK1
        3 Product Term(s)
        1 GLB Level(s)

        MZ0Z0.D = (!MZ0Z0 & !COUTAZ0Z_3
            # COUT0Z0Z_0 & COUT0Z0Z_3 & COUTAZ0Z_3 & !COUT0Z0Z_1
            & !COUT0Z0Z_2)
            $ VCC
        MZ0Z0.C = BUF_2760
        MZ0Z0.R = COUTAZ0Z_0 & COUTAZ0Z_1 & COUTAZ0Z_2 & !COUTAZ0Z_3

    Output CHOICE_1_C_4

        2 Input(s)
            UN1_COUNT_IZ0, CHOICE_1_C_4
        2 Fanout(s)
            glb01.I17, CHOICE(4).IR
        2 Product Term(s)
        2 GLB Level(s)

        CHOICE_1_C_4 = CHOICE_1_C_4 & !UN1_COUNT_IZ0
            # !UN1_COUNT_IZ0

    Output CHOICE_1_C_3

        2 Input(s)
            N_950, CHOICE_1_C_3
        2 Fanout(s)
            glb01.I8, CHOICE(3).IR
        2 Product Term(s)
        2 GLB Level(s)

        CHOICE_1_C_3 = CHOICE_1_C_3 & !N_950
            # !N_950

    Output BUF_2760

        1 Input(s)
            XCLKX
        2 Fanout(s)
            glb15.CLK2, glb01.CLK2
        1 Product Term(s)
        1 GLB Level(s)

        BUF_2760 = XCLKX


GLB glb02, D1

    4 Input(s)
        (glb04.O0, TEMPZ0Z_0, I11), (glb21.O1, TEMPZ0Z_1, I13), 
        (glb05.O1, TEMPZ0Z_2, I6), (glb21.O0, TEMPZ0Z_3, I12)
    4 Output(s)
        (OR_2280, O3), (OR_2278, O0), (OR_2277, O1), (OR_1269, O2)
    13 Product Term(s)

    Output OR_2280

        4 Input(s)
            TEMPZ0Z_3, TEMPZ0Z_2, TEMPZ0Z_1, TEMPZ0Z_0
        1 Fanout(s)
            DATA(1).IR
        3 Product Term(s)
        1 GLB Level(s)

        OR_2280 = TEMPZ0Z_1 & TEMPZ0Z_3
            # TEMPZ0Z_0 & TEMPZ0Z_1 & TEMPZ0Z_2
            # !TEMPZ0Z_1 & !TEMPZ0Z_2 & !TEMPZ0Z_3

    Output OR_2278

        4 Input(s)
            TEMPZ0Z_3, TEMPZ0Z_2, TEMPZ0Z_1, TEMPZ0Z_0
        1 Fanout(s)
            DATA(7).IR
        3 Product Term(s)
        1 GLB Level(s)

        OR_2278 = TEMPZ0Z_1 & TEMPZ0Z_3
            # TEMPZ0Z_2 & !TEMPZ0Z_0 & !TEMPZ0Z_1 & !TEMPZ0Z_3
            # TEMPZ0Z_0 & !TEMPZ0Z_1 & !TEMPZ0Z_2 & !TEMPZ0Z_3

    Output OR_2277

        4 Input(s)
            TEMPZ0Z_3, TEMPZ0Z_2, TEMPZ0Z_1, TEMPZ0Z_0
        1 Fanout(s)
            DATA(6).IR
        3 Product Term(s)
        1 GLB Level(s)

        OR_2277 = TEMPZ0Z_1 & TEMPZ0Z_3
            # TEMPZ0Z_1 & TEMPZ0Z_2 & !TEMPZ0Z_0
            # TEMPZ0Z_0 & TEMPZ0Z_2 & !TEMPZ0Z_1 & !TEMPZ0Z_3

    Output OR_1269

        4 Input(s)
            TEMPZ0Z_3, TEMPZ0Z_2, TEMPZ0Z_1, TEMPZ0Z_0
        1 Fanout(s)
            DATA(2).IR
        4 Product Term(s)
        1 GLB Level(s)

        OR_1269 = TEMPZ0Z_3 & !TEMPZ0Z_1
            # TEMPZ0Z_2 & !TEMPZ0Z_1
            # !TEMPZ0Z_0 & !TEMPZ0Z_1
            # TEMPZ0Z_2 & !TEMPZ0Z_0 & !TEMPZ0Z_3


GLB glb03, D6

    4 Input(s)
        (glb04.O0, TEMPZ0Z_0, I11), (glb21.O1, TEMPZ0Z_1, I13), 
        (glb05.O1, TEMPZ0Z_2, I6), (glb21.O0, TEMPZ0Z_3, I12)
    4 Output(s)
        (OR_2279, O2), (OR_2275, O3), (DATA_1_C_0, O1), (AND_2276, O0)
    9 Product Term(s)

    Output OR_2279

        4 Input(s)
            TEMPZ0Z_3, TEMPZ0Z_2, TEMPZ0Z_1, TEMPZ0Z_0
        1 Fanout(s)
            DATA(4).IR
        4 Product Term(s)
        1 GLB Level(s)

        OR_2279 = TEMPZ0Z_1 & TEMPZ0Z_3
            # TEMPZ0Z_0 & TEMPZ0Z_1 & TEMPZ0Z_2
            # TEMPZ0Z_2 & !TEMPZ0Z_0 & !TEMPZ0Z_1 & !TEMPZ0Z_3
            # TEMPZ0Z_0 & !TEMPZ0Z_1 & !TEMPZ0Z_2 & !TEMPZ0Z_3

    Output OR_2275

        4 Input(s)
            TEMPZ0Z_3, TEMPZ0Z_2, TEMPZ0Z_1, TEMPZ0Z_0
        1 Fanout(s)
            DATA(3).IR
        3 Product Term(s)
        1 GLB Level(s)

        OR_2275 = TEMPZ0Z_0
            # TEMPZ0Z_1 & TEMPZ0Z_3
            # TEMPZ0Z_2 & !TEMPZ0Z_1 & !TEMPZ0Z_3

    Output DATA_1_C_0

        2 Input(s)
            TEMPZ0Z_3, TEMPZ0Z_1
        1 Fanout(s)
            DATA(0).IR
        1 Product Term(s)
        1 GLB Level(s)

        DATA_1_C_0 = TEMPZ0Z_1 & TEMPZ0Z_3

    Output AND_2276

        3 Input(s)
            TEMPZ0Z_2, TEMPZ0Z_1, TEMPZ0Z_0
        1 Fanout(s)
            DATA(5).IR
        1 Product Term(s)
        1 GLB Level(s)

        AND_2276 = TEMPZ0Z_1 & !TEMPZ0Z_0 & !TEMPZ0Z_2