frequent.vm

这是个用VHDL写的测频源程序,最大可测10M,你可以任意修改,但请你更新后发一份给我

//
// Written by Synplify
// Sat Jun 02 15:12:26 2001
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\e:\isptools\synplify\lib\vhd\std.vhd "
// file 2 "\c:\my documents\shudianku\frequent\frequent.vhd "
// file 3 "\e:\isptools\synplify\lib\vhd\std1164.vhd "
// file 4 "\e:\isptools\synplify\lib\vhd\arith.vhd "
// file 5 "\e:\isptools\synplify\lib\vhd\unsigned.vhd "

`timescale 100 ps/100 ps
module DFF_FD (
  Q,
  D,
  CP,
  R
);
output Q;
input D;
input CP;
input R;
wire Q ;
wire D ;
wire CP ;
wire R ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  reg r_e_g0; // dffr
  always @(posedge CP or posedge R ) r_e_g0 = #1 R ? 1'b0 : D ;
    assign Q = r_e_g0;
endmodule /* DFF_FD */

module FD11 (
  Q0,
  D0,
  CLK
);
output Q0;
input D0;
input CLK;
wire Q0 ;
wire D0 ;
wire CLK ;
wire false ;
wire true ;
  DFF_FD blk2 (
	.Q(Q0),
	.D(D0),
	.CP(CLK),
	.R(false)
);
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* FD11 */

module FD21 (
  Q0,
  D0,
  CLK,
  CD
);
output Q0;
input D0;
input CLK;
input CD;
wire Q0 ;
wire D0 ;
wire CLK ;
wire CD ;
wire true ;
wire false ;
  DFF_FD blk2 (
	.Q(Q0),
	.D(D0),
	.CP(CLK),
	.R(CD)
);
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* FD21 */

module XOR2 (
  Z0,
  A0,
  A1
);
output Z0;
input A0;
input A1;
wire Z0 ;
wire A0 ;
wire A1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  Z0 = A0  ^ A1 ;
endmodule /* XOR2 */

module AND2 (
  Z0,
  A0,
  A1
);
output Z0;
input A0;
input A1;
wire Z0 ;
wire A0 ;
wire A1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  Z0 = A0  & A1 ;
endmodule /* AND2 */

module OR2 (
  Z0,
  A0,
  A1
);
output Z0;
input A0;
input A1;
wire Z0 ;
wire A0 ;
wire A1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  Z0 = A0  | A1 ;
endmodule /* OR2 */

module XINPUT (
  Z0,
  XI0
);
output Z0;
input XI0;
wire Z0 ;
wire XI0 ;
wire true ;
wire false ;
  assign #(1)  Z0 = XI0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* XINPUT */

module IB11 (
  Z0,
  XI0
);
output Z0;
input XI0;
wire Z0 ;
wire XI0 ;
wire true ;
wire false ;
  XINPUT \\$1I45  (
	.Z0(Z0),
	.XI0(XI0)
);
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* IB11 */

module XOUTPUT (
  XO0,
  A0
);
output XO0;
input A0;
wire XO0 ;
wire A0 ;
wire true ;
wire false ;
  assign #(1)  XO0 = A0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* XOUTPUT */

module OB11 (
  XO0,
  A0
);
output XO0;
input A0;
wire XO0 ;
wire A0 ;
wire true ;
wire false ;
  XOUTPUT \\$1I42  (
	.XO0(XO0),
	.A0(A0)
);
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* OB11 */

module INV (
  ZN0,
  A0
);
output ZN0;
input A0;
wire ZN0 ;
wire A0 ;
wire true ;
wire false ;
  assign #(1)  ZN0 = ~ A0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* INV */

module MUX2 (
  Z0,
  A0,
  A1,
  S0
);
output Z0;
input A0;
input A1;
input S0;
wire Z0 ;
wire A0 ;
wire A1 ;
wire S0 ;
wire true ;
wire false ;
wire \$1N8  ;
wire \$1N22  ;
wire \$1N6  ;
  AND2 \\$1I25  (
	.Z0(\$1N6 ),
	.A0(A0),
	.A1(\$1N22 )
);
  AND2 \\$1I31  (
	.Z0(\$1N8 ),
	.A0(A1),
	.A1(S0)
);
  OR2 \\$1I35  (
	.Z0(Z0),
	.A0(\$1N6 ),
	.A1(\$1N8 )
);
  INV \\$1I38  (
	.ZN0(\$1N22 ),
	.A0(S0)
);
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* MUX2 */

module AND3 (
  Z0,
  A0,
  A1,
  A2
);
output Z0;
input A0;
input A1;
input A2;
wire Z0 ;
wire A0 ;
wire A1 ;
wire A2 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  Z0 = A0  & A1  & A2 ;
endmodule /* AND3 */

module OR4 (
  Z0,
  A0,
  A1,
  A2,
  A3
);
output Z0;
input A0;
input A1;
input A2;
input A3;
wire Z0 ;
wire A0 ;
wire A1 ;
wire A2 ;
wire A3 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  Z0 = A0  | A1  | A2  | A3 ;
endmodule /* OR4 */

module BUF (
  Z0,
  A0
);
output Z0;
input A0;
wire Z0 ;
wire A0 ;
wire true ;
wire false ;
  assign #(1)  Z0 = A0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* BUF */

module LD41 (
  Q0,
  D0,
  G,
  PD,
  CD
);
output Q0;
input D0;
input G;
input PD;
input CD;
wire Q0 ;
wire D0 ;
wire G ;
wire PD ;
wire CD ;
wire true ;
wire false ;
wire \$1N288  ;
wire \$1N188  ;
wire \$1N293  ;
wire \$1N159  ;
wire \$1N166  ;
wire \$1N6  ;
wire \$1N223  ;
  INV \\$1I226  (
	.ZN0(\$1N223 ),
	.A0(CD)
);
  AND3 \\$1I277  (
	.Z0(\$1N166 ),
	.A0(\$1N6 ),
	.A1(\$1N223 ),
	.A2(D0)
);
  AND3 \\$1I278  (
	.Z0(\$1N159 ),
	.A0(\$1N6 ),
	.A1(\$1N223 ),
	.A2(\$1N293 )
);
  AND3 \\$1I279  (
	.Z0(\$1N188 ),
	.A0(D0),
	.A1(\$1N223 ),
	.A2(G)
);
  AND2 \\$1I284  (
	.Z0(\$1N288 ),
	.A0(\$1N223 ),
	.A1(PD)
);
  OR4 \\$1I287  (
	.Z0(\$1N6 ),
	.A0(\$1N166 ),
	.A1(\$1N159 ),
	.A2(\$1N188 ),
	.A3(\$1N288 )
);
  INV \\$1I292  (
	.ZN0(\$1N293 ),
	.A0(G)
);
  BUF \\$1I314  (
	.Z0(Q0),
	.A0(\$1N6 )
);
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* LD41 */

module frequent (
  xclk,
  clk,
  clk1,
  data,
  choice
);
input xclk;
input clk;
input clk1;
output [7:0] data;
output [5:0] choice;
wire xclk ;
wire clk ;
wire clk1 ;
wire [7:0] data;
wire [5:0] choice;
wire [3:0] couta;
wire [3:0] cout0;
wire [3:0] cout1;
wire [3:0] cout2;
wire [3:0] cout3;
wire [3:0] cout4;
wire [3:0] cout5;
wire [3:0] cout6;
wire [2:0] count;
wire [3:0] temp;
wire [3:1] un4_count;
wire [3:0] count6;
wire [4:1] un5_cout0;
wire [4:1] un5_cout1;
wire [4:1] un5_cout2;
wire [4:1] un5_cout3;
wire [4:1] un5_cout4;
wire [4:1] un5_cout5;
wire [4:1] un5_cout6;
wire [3:0] count0;
wire [3:0] count5;
wire [3:0] count4;
wire [3:0] count3;
wire [3:0] count2;
wire [3:0] count1;
wire [2:0] temp_11;
wire [2:1] count_3;
wire [2:0] count_i;
wire [3:0] couta_i;
wire [3:1] count0_i_0;
wire [3:1] count1_i_0;
wire [3:0] count6_i_0;
wire [3:1] count2_i_0;
wire [3:1] count3_i_0;
wire [3:1] count4_i_0;
wire [3:1] count5_i_0;
wire [2:1] cout0_i;
wire [2:1] cout1_i;
wire [2:1] cout2_i;
wire [2:1] cout3_i;
wire [2:1] cout4_i;
wire [2:1] cout5_i;
wire [2:1] cout6_i;
wire [3:0] temp_i_0;
wire [0:0] data_1_c;
wire [5:0] choice_1_c;
wire [0:0] data_1_c_i;
wire [3:1] temp_11_iv_i;
wire m0 ;
wire m1 ;
wire m2 ;
wire m3 ;
wire m4 ;
wire m5 ;
wire un1_count ;
wire un4_count6 ;
wire VCC ;
wire GND ;
wire couta_n1 ;
wire couta_n2 ;
wire couta_n3 ;
wire N_61 ;
wire N_65 ;
wire N_69 ;
wire N_70 ;
wire N_71 ;
wire N_72 ;
wire N_73 ;
wire N_74 ;
wire N_75 ;
wire N_76 ;
wire N_77 ;
wire N_78 ;
wire N_79 ;
wire N_80 ;
wire N_84 ;
wire N_88 ;
wire N_91 ;
wire N_97 ;
wire N_101 ;
wire N_104 ;
wire N_110 ;
wire N_114 ;
wire N_117 ;
wire N_123 ;
wire N_127 ;
wire N_130 ;
wire N_136 ;
wire N_140 ;
wire N_143 ;
wire N_149 ;
wire N_153 ;
wire N_156 ;
wire N_162 ;
wire N_166 ;
wire N_169 ;
wire N_173 ;
wire N_174 ;
wire N_175 ;
wire N_176 ;
wire N_177 ;
wire N_178 ;
wire N_179 ;
wire N_180 ;
wire N_197 ;
wire N_198 ;
wire N_201 ;
wire N_202 ;
wire N_203 ;
wire N_204 ;
wire N_206 ;
wire N_207 ;
wire N_208 ;
wire N_209 ;
wire N_210 ;
wire N_211 ;
wire N_212 ;
wire N_213 ;
wire N_214 ;
wire N_638 ;
wire N_816 ;
wire N_817 ;
wire N_818 ;
wire N_819 ;
wire N_829 ;
wire N_830 ;
wire N_831 ;
wire N_832 ;
wire N_833 ;
wire N_834 ;
wire N_835 ;
wire N_836 ;
wire N_837 ;
wire N_838 ;
wire N_839 ;
wire N_840 ;
wire N_841 ;
wire N_842 ;
wire N_843 ;
wire N_844 ;
wire N_845 ;
wire N_846 ;
wire N_847 ;
wire N_848 ;
wire N_849 ;
wire N_850 ;
wire N_851 ;
wire N_852 ;
wire N_853 ;
wire N_854 ;
wire N_855 ;
wire N_856 ;
wire N_857 ;
wire N_858 ;
wire N_859 ;
wire N_860 ;
wire N_861 ;
wire N_862 ;
wire N_863 ;
wire N_864 ;
wire N_865 ;
wire N_866 ;
wire N_867 ;
wire N_868 ;
wire N_869 ;
wire N_870 ;
wire N_871 ;
wire N_872 ;
wire N_873 ;
wire N_874 ;
wire N_875 ;
wire N_876 ;
wire N_877 ;
wire N_878 ;
wire N_879 ;
wire N_880 ;
wire N_881 ;
wire N_882 ;
wire N_883 ;
wire N_884 ;
wire N_906 ;
wire N_907 ;
wire N_908 ;
wire N_909 ;
wire N_910 ;
wire N_911 ;
wire N_912 ;
wire N_913 ;
wire N_914 ;
wire N_915 ;
wire N_916 ;
wire N_917 ;
wire N_918 ;
wire N_919 ;
wire N_920 ;
wire N_921 ;
wire N_922 ;
wire N_923 ;
wire N_924 ;
wire N_925 ;
wire N_926 ;
wire N_927 ;
wire N_928 ;
wire N_929 ;
wire N_930 ;
wire N_931 ;
wire N_932 ;
wire N_933 ;
wire N_934 ;
wire N_935 ;
wire N_936 ;
wire N_937 ;
wire N_938 ;
wire N_939 ;
wire N_940 ;
wire N_941 ;
wire N_942 ;
wire N_943 ;
wire N_944 ;
wire N_945 ;
wire N_947 ;
wire N_948 ;
wire N_949 ;
wire N_950 ;
wire N_951 ;
wire N_952 ;
wire N_955 ;
wire N_956 ;
wire N_957 ;
wire N_958 ;
wire N_959 ;
wire N_960 ;
wire N_961 ;
wire N_962 ;
wire N_963 ;
wire N_964 ;
wire N_965 ;
wire N_966 ;
wire N_967 ;
wire N_968 ;
wire N_1095 ;
wire N_1096 ;
wire N_1097 ;
wire N_1098 ;
wire N_1099 ;
wire N_1100 ;
wire N_1101 ;
wire p7_un10_couta ;
wire m5_i ;
wire m4_i ;
wire m3_i ;
wire m2_i ;
wire m1_i ;
wire m0_i ;
wire un4_count6_i ;
wire un1_count_i ;
wire N_911_i ;
wire N_910_i ;
wire N_909_i ;
wire N_908_i ;
wire N_907_i ;
wire N_906_i ;
wire xclk_c ;
wire clk_c ;
wire clk1_c ;
wire N_209_i_0_c ;
wire N_1108 ;
wire N_918_i ;
wire N_916_i ;
wire N_917_i ;
wire N_914_i ;
wire N_915_i ;
wire N_912_i ;
wire N_913_i ;
wire N_1114 ;
wire N_925_i ;
wire N_923_i ;
wire N_924_i ;
wire N_921_i ;
wire N_922_i ;
wire N_919_i ;
wire N_920_i ;
wire N_932_i ;
wire N_930_i ;
wire N_931_i ;
wire N_928_i ;
wire N_929_i ;
wire N_926_i ;
wire N_927_i ;
wire N_939_i ;
wire N_937_i ;
wire N_938_i ;
wire N_935_i ;
wire N_936_i ;
wire N_933_i ;
wire N_934_i ;
wire N_958_i ;
wire N_959_i ;
wire N_1132 ;
wire N_968_i ;
wire N_957_i ;
wire N_1133 ;
wire N_955_i ;
wire N_956_i ;
wire N_1134 ;
wire N_1135 ;
wire N_947_i ;
wire N_945_i ;
wire N_1095_i ;
wire N_944_i ;
wire N_1096_i ;
wire N_1097_i ;
wire N_943_i ;
wire N_1098_i ;
wire N_942_i ;
wire N_1099_i ;
wire N_941_i ;
wire N_1100_i ;
wire N_940_i ;
wire N_1101_i ;
wire N_210_i ;
wire N_1153 ;
wire N_211_i ;
wire N_1154 ;
wire N_212_i ;
wire N_207_i ;
wire N_208_i ;
wire N_206_i ;
wire N_213_i ;
wire N_203_i ;
wire N_204_i ;
wire N_201_i ;
wire N_202_i ;
wire N_23_i_c ;
wire N_25_i_c ;
wire N_27_i_c ;
wire N_29_i_c ;
wire N_33_i_c ;
wire N_193_i_0_c ;
wire N_638_i_0 ;
wire N_194_i ;
wire N_312_i_0 ;
wire N_308_i_0 ;
wire N_304_i_0 ;
wire N_300_i_0 ;
wire N_296_i_0 ;
wire N_292_i_0 ;
wire N_342_i_0 ;
wire N_338_i_0 ;
wire N_334_i_0 ;
wire N_330_i_0 ;
wire N_616_i_0 ;
wire N_324_i_0 ;
wire N_320_i_0 ;
wire N_316_i_0 ;
wire N_637_i_0 ;
wire N_1201 ;
wire N_1202 ;
wire N_1203 ;
wire N_1204 ;
wire N_1205 ;
wire N_1206 ;
wire N_1207 ;
wire N_1208 ;
wire N_1209 ;
wire N_1210 ;
wire N_1211 ;
wire N_1212 ;
wire N_1213 ;
wire N_1214 ;
wire N_1215 ;
wire N_1216 ;
wire N_1217 ;
wire N_1218 ;
wire N_1219 ;
wire N_1220 ;
wire N_1221 ;
wire N_1222 ;
wire N_1223 ;
wire N_1224 ;
wire N_1225 ;
wire N_1226 ;
wire N_1227 ;
wire N_1228 ;
wire N_1229 ;
wire N_1230 ;
wire N_1231 ;
wire N_1232 ;
wire N_1233 ;
wire N_1234 ;
wire N_1235 ;
wire N_1236 ;
wire N_1237 ;
wire N_1238 ;
wire N_1239 ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @2:155
  FD11 \count_Z[2]  (
	.Q0(count[2]),
	.D0(count_3[2]),
	.CLK(clk_c)
);
// @2:142
  FD11 \count3_Z[3]  (
	.Q0(count3[3]),
	.D0(N_875),
	.CLK(clk_c)
);
// @2:142
  FD11 \count4_Z[0]  (
	.Q0(count4[0]),
	.D0(N_869),
	.CLK(clk_c)
);
// @2:142
  FD11 \count4_Z[1]  (
	.Q0(count4[1]),
	.D0(N_870),
	.CLK(clk_c)
);
// @2:142
  FD11 \count4_Z[2]  (
	.Q0(count4[2]),
	.D0(N_871),
	.CLK(clk_c)
);
// @2:142
  FD11 \count4_Z[3]  (
	.Q0(count4[3]),
	.D0(N_884),
	.CLK(clk_c)
);
// @2:142
  FD11 \count5_Z[0]  (
	.Q0(count5[0]),
	.D0(N_865),
	.CLK(clk_c)