📄 clock.lst
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AVRASM ver. 1.76.4 d:\avr program\led colock\clock.asm Fri Dec 30 18:41:05 2005
;******************************** AVR program ***********************************
;*
;* Title : clock display
;* Verion : V01
;* OSC : 4MHz
;* Last update: 2005.12.29
;* Author : Sonic
;* Description: The program is suitable for AT90S2313
;*
;********************************************************************************
;************************* Regsister definition *********************************
;*
.include"2313def.inc"
;***************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number :AVR000
;* File Name :"2313def.inc"
;* Title :Register/Bit Definitions for the AT90S2313
;* Date :99.01.28
;* Version :1.30
;* Support telephone :+47 72 88 43 88 (ATMEL Norway)
;* Support fax :+47 72 88 43 99 (ATMEL Norway)
;* Support E-Mail :avr@atmel.com
;* Target MCU :AT90S2313
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;*
;* The Register names are represented by their hexadecimal addresses.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;***************************************************************************
;***** Specify Device
.device AT90S2313
;***** I/O Register Definitions
.equ SREG =$3f
.equ SPL =$3d
.equ GIMSK =$3b
.equ GIFR =$3a
.equ TIMSK =$39
.equ TIFR =$38
.equ MCUCR =$35
.equ TCCR0 =$33
.equ TCNT0 =$32
.equ TCCR1A =$2f
.equ TCCR1B =$2e
.equ TCNT1H =$2d
.equ TCNT1L =$2c
.equ OCR1AH =$2b
.equ OCR1AL =$2a
.equ ICR1H =$25
.equ ICR1L =$24
.equ WDTCR =$21
.equ EEAR =$1e
.equ EEARL =$1e
.equ EEDR =$1d
.equ EECR =$1c
.equ PORTB =$18
.equ DDRB =$17
.equ PINB =$16
.equ PORTD =$12
.equ DDRD =$11
.equ PIND =$10
.equ UDR =$0c
.equ USR =$0b
.equ UCR =$0a
.equ UBRR =$09
.equ ACSR =$08
;***** Bit Definitions
.equ SP7 =7
.equ SP6 =6
.equ SP5 =5
.equ SP4 =4
.equ SP3 =3
.equ SP2 =2
.equ SP1 =1
.equ SP0 =0
.equ INT1 =7
.equ INT0 =6
.equ INTF1 =7
.equ INTF0 =6
.equ TOIE1 =7
.equ OCIE1A =6
.equ TICIE =3
.equ TOIE0 =1
.equ TOV1 =7
.equ OCF1A =6
.equ ICF1 =3
.equ TOV0 =1
.equ SE =5
.equ SM =4
.equ ISC11 =3
.equ ISC10 =2
.equ ISC01 =1
.equ ISC00 =0
.equ CS02 =2
.equ CS01 =1
.equ CS00 =0
.equ COM1A1 =7
.equ COM1A0 =6
.equ PWM11 =1
.equ PWM10 =0
.equ ICNC1 =7
.equ ICES1 =6
.equ CTC1 =3
.equ CS12 =2
.equ CS11 =1
.equ CS10 =0
.equ WDTOE =4
.equ WDE =3
.equ WDP2 =2
.equ WDP1 =1
.equ WDP0 =0
.equ EEMWE =2
.equ EEWE =1
.equ EERE =0
.equ PB7 =7
.equ PB6 =6
.equ PB5 =5
.equ PB4 =4
.equ PB3 =3
.equ PB2 =2
.equ PB1 =1
.equ PB0 =0
.equ DDB7 =7
.equ DDB6 =6
.equ DDB5 =5
.equ DDB4 =4
.equ DDB3 =3
.equ DDB2 =2
.equ DDB1 =1
.equ DDB0 =0
.equ PINB7 =7
.equ PINB6 =6
.equ PINB5 =5
.equ PINB4 =4
.equ PINB3 =3
.equ PINB2 =2
.equ PINB1 =1
.equ PINB0 =0
.equ PD6 =6
.equ PD5 =5
.equ PD4 =4
.equ PD3 =3
.equ PD2 =2
.equ PD1 =1
.equ PD0 =0
.equ DDD6 =6
.equ DDD5 =5
.equ DDD4 =4
.equ DDD3 =3
.equ DDD2 =2
.equ DDD1 =1
.equ DDD0 =0
.equ PIND6 =6
.equ PIND5 =5
.equ PIND4 =4
.equ PIND3 =3
.equ PIND2 =2
.equ PIND1 =1
.equ PIND0 =0
.equ RXC =7
.equ TXC =6
.equ UDRE =5
.equ FE =4
.equ OR =3
.equ RXCIE =7
.equ TXCIE =6
.equ UDRIE =5
.equ RXEN =4
.equ TXEN =3
.equ CHR9 =2
.equ RXB8 =1
.equ TXB8 =0
.equ ACD =7
.equ ACO =5
.equ ACI =4
.equ ACIE =3
.equ ACIC =2
.equ ACIS1 =1
.equ ACIS0 =0
.def XL =r26
.def XH =r27
.def YL =r28
.def YH =r29
.def ZL =r30
.def ZH =r31
.equ RAMEND =$DF ;Last On-Chip SRAM Location
.equ XRAMEND =$DF
.equ E2END =$7F
.equ FLASHEND=$3FF
.equ INT0addr=$001 ;External Interrupt0 Vector Address
.equ INT1addr=$002 ;External Interrupt1 Vector Address
.equ ICP1addr=$003 ;Input Capture1 Interrupt Vector Address
.equ OC1addr =$004 ;Output Compare1 Interrupt Vector Address
.equ OVF1addr=$005 ;Overflow1 Interrupt Vector Address
.equ OVF0addr=$006 ;Overflow0 Interrupt Vector Address
.equ URXCaddr=$007 ;UART Receive Complete Interrupt Vector Address
.equ UDREaddr=$008 ;UART Data Register Empty Interrupt Vector Address
.equ UTXCaddr=$009 ;UART Transmit Complete Interrupt Vector Address
.equ ACIaddr =$00a ;Analog Comparator Interrupt Vector Address
.def tempff = r16
.def temp00 = r17
.def temp08 = r18
.def temprs = r19
.def temp = r20
.def delay1 = r21
.def delay2 = r22
.def delay3 = r23
.def counter = r24
;*
;********************************************************************************
;********************Program code************************************************
;*
.org $0000
000000 c00a rjmp reset ; reset ports
000001 9518 reti ; INT0 ports( no useing )
000002 9518 reti ; INT1 ports( no useing )
000003 9518 reti ; Timer1 capture ports(no useing )
000004 9518 reti ; Timer1 compare ports( no useing )
000005 9518 reti ; Timer1 overflow ports( no useing )
000006 9518 reti ; Timer0 overflow ports( no useing )
000007 9518 reti ; UART RX complete ports( no useing )
000008 9518 reti ; UDR Empty ports( no useing )
000009 9518 reti ; UART TX complete ports( no useing )
00000a 9518 reti ; Analog comparator ports( no useing )
.org $000b
reset:
00000b ed4f ldi temp, low(ramend) ;set stack address
00000c bf4d out spl, temp
00000d ef0f ser tempff
00000e bb01 out ddrd, tempff
00000f 2711 clr temp00
000010 bb17 out ddrb, temp00
000011 bb18 out portb, temp00
000012 e028 ldi temp08, $08
cycle:
000013 bb22 out portd, temp08
000014 e348 ldi temp, $38 ; LCD system funtion set
000015 e030 ldi temprs, $00 ; prepare writeing instruction to LCD
000016 d01c rcall write
000017 e04c ldi temp, $0c ; LCD display ON/OFF control set
000018 d01a rcall write
000019 e041 ldi temp, $01 ; LCD display clear set
00001a d018 rcall write
00001b e046 ldi temp, $06 ; LCD entry mode set
00001c d016 rcall write
00001d e840 ldi temp, $80 ; set the first DD RAM address is $00
00001e d014 rcall write
00001f ebea ldi zl, low(chatble*2) ; set ROM address cursor
000020 e0f0 ldi zh, high(chatble*2)
000021 e130 ldi temprs, 0b00010000 ; prepare writeing data to LCD
000022 e180 ldi counter, 16 ; set counter initial value
000023 d01d rcall display
000024 2733 clr temprs
000025 ec40 ldi temp, $c0 ; set DD RAM address is $40
000026 d00c rcall write
000027 e130 ldi temprs, 0b00010000 ; prepare writeing data to LCD
000028 e180 ldi counter, 16
000029 d017 rcall display ; transfer display
00002a d028 rcall delay ; transfer delay
00002b e180 ldi counter, 16 ; resume counter initial value
00002c 2733 clr temprs ; prepare writeing instruction to LCD
go_on:
00002d e148 ldi temp, $18 ; LCD replacement set
00002e d004 rcall write ; transfer write
00002f d023 rcall delay
000030 958a dec counter
000031 f7d9 brne go_on
000032 cfe0 rjmp cycle
write:
000033 9a92 sbi portd, 2
000034 d013 rcall delay1us
busy:
000035 99b7 sbic pinb, 7 ; check BF =0 ?
000036 cffe rjmp busy
000037 bb32 out portd, temprs
000038 bb07 out ddrb, tempff ; set pb as output ports
000039 9a92 sbi portd, 2
00003a bb48 out portb, temp
00003b d010 rcall delay2ms ; transfer delay2ms
00003c 9892 cbi portd, 2 ; E=0
00003d bb17 out ddrb, temp00 ; set pb as input ports
00003e bb18 out portb, temp00
00003f bb22 out portd, temp08
000040 9508 ret
display:
000041 95c8 lpm ; from ROM read data
000042 2d40 mov temp, r0
000043 dfef rcall write
000044 9631 adiw zl, 1
000045 958a dec counter
000046 f7d1 brne display
000047 9508 ret
delay1us:
000048 e052 ldi delay1, 2 ; delay1us
000049 955a dec delay1
00004a f7f1 brne delay1us+1
00004b 9508 ret
delay2ms:
00004c e05a ldi delay1, 10 ; delay2ms
00004d ef6a ldi delay2, 250
00004e 956a dec delay2
00004f f7f1 brne delay2ms+2
000050 955a dec delay1
000051 f7d9 brne delay2ms+1
000052 9508 ret
delay:
000053 e654 ldi delay1, $64 ; delay about 600ms
000054 e860 ldi delay2, $80
000055 e870 ldi delay3, $80
000056 957a dec delay3
000057 f7f1 brne delay+3
000058 956a dec delay2
000059 f7d9 brne delay+2
00005a 955a dec delay1
00005b f7c1 brne delay+1
00005c 9508 ret
chatble:
.db $57, $45, $4c, $43, $4f, $4d, $45, $20
00005d 4557
00005e 434c
00005f 4d4f
000060 2045
.db $54, $4f, $20, $54, $48, $45, $20, $20
000061 4f54
000062 5420
000063 4548
000064 2020
.db $41, $56, $52, $20, $57, $4f, $52, $4c
000065 5641
000066 2052
000067 4f57
000068 4c52
.db $44, $20, $21, $20, $20, $20, $20, $20
000069 2044
00006a 2021
00006b 2020
00006c 2020
Assembly complete with no errors.
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