📄 cplcd.lst
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.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
.equ WGM12 = 3 ; Waveform Generation Mode
.equ CTC10 = WGM12 ; For compatibility
.equ CTC1 = WGM12 ; For compatibility
.equ WGM13 = 4 ; Waveform Generation Mode
.equ CTC11 = WGM13 ; For compatibility
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
; ***** TIMER_COUNTER_2 **************
; TIMSK - Timer/Counter Interrupt Mask register
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
; TIFR - Timer/Counter Interrupt Flag Register
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
.equ OCF2 = 7 ; Output Compare Flag 2
; TCCR2 - Timer/Counter2 Control Register
.equ CS20 = 0 ; Clock Select bit 0
.equ CS21 = 1 ; Clock Select bit 1
.equ CS22 = 2 ; Clock Select bit 2
.equ WGM21 = 3 ; Waveform Generation Mode
.equ CTC2 = WGM21 ; For compatibility
.equ COM20 = 4 ; Compare Output Mode bit 0
.equ COM21 = 5 ; Compare Output Mode bit 1
.equ WGM20 = 6 ; Waveform Genration Mode
.equ PWM2 = WGM20 ; For compatibility
.equ FOC2 = 7 ; Force Output Compare
; TCNT2 - Timer/Counter2
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
; OCR2 - Timer/Counter2 Output Compare Register
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
; ASSR - Asynchronous Status Register
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
.equ AS2 = 3 ; Asynchronous Timer/counter2
; SFIOR - Special Function IO Register
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
; ***** USART ************************
; UDR - USART I/O Data Register
.equ UDR0 = 0 ; USART I/O Data Register bit 0
.equ UDR1 = 1 ; USART I/O Data Register bit 1
.equ UDR2 = 2 ; USART I/O Data Register bit 2
.equ UDR3 = 3 ; USART I/O Data Register bit 3
.equ UDR4 = 4 ; USART I/O Data Register bit 4
.equ UDR5 = 5 ; USART I/O Data Register bit 5
.equ UDR6 = 6 ; USART I/O Data Register bit 6
.equ UDR7 = 7 ; USART I/O Data Register bit 7
; UCSRA - USART Control and Status Register A
.equ USR = UCSRA ; For compatibility
.equ MPCM = 0 ; Multi-processor Communication Mode
.equ U2X = 1 ; Double the USART transmission speed
.equ UPE = 2 ; Parity Error
.equ PE = UPE ; For compatibility
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; USART Data Register Empty
.equ TXC = 6 ; USART Transmitt Complete
.equ RXC = 7 ; USART Receive Complete
; UCSRB - USART Control and Status Register B
.equ UCR = UCSRB ; For compatibility
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ UCSZ2 = 2 ; Character Size
.equ CHR9 = UCSZ2 ; For compatibility
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
; UCSRC - USART Control and Status Register C
.equ UCPOL = 0 ; Clock Polarity
.equ UCSZ0 = 1 ; Character Size
.equ UCSZ1 = 2 ; Character Size
.equ USBS = 3 ; Stop Bit Select
.equ UPM0 = 4 ; Parity Mode Bit 0
.equ UPM1 = 5 ; Parity Mode Bit 1
.equ UMSEL = 6 ; USART Mode Select
.equ URSEL = 7 ; Register Select
.equ UBRRHI = UBRRH ; For compatibility
; ***** TWI **************************
; TWBR - TWI Bit Rate register
.equ I2BR = TWBR ; For compatibility
.equ TWBR0 = 0 ;
.equ TWBR1 = 1 ;
.equ TWBR2 = 2 ;
.equ TWBR3 = 3 ;
.equ TWBR4 = 4 ;
.equ TWBR5 = 5 ;
.equ TWBR6 = 6 ;
.equ TWBR7 = 7 ;
; TWCR - TWI Control Register
.equ I2CR = TWCR ; For compatibility
.equ TWIE = 0 ; TWI Interrupt Enable
.equ I2IE = TWIE ; For compatibility
.equ TWEN = 2 ; TWI Enable Bit
.equ I2EN = TWEN ; For compatibility
.equ ENI2C = TWEN ; For compatibility
.equ TWWC = 3 ; TWI Write Collition Flag
.equ I2WC = TWWC ; For compatibility
.equ TWSTO = 4 ; TWI Stop Condition Bit
.equ I2STO = TWSTO ; For compatibility
.equ TWSTA = 5 ; TWI Start Condition Bit
.equ I2STA = TWSTA ; For compatibility
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
.equ I2EA = TWEA ; For compatibility
.equ TWINT = 7 ; TWI Interrupt Flag
.equ I2INT = TWINT ; For compatibility
; TWSR - TWI Status Register
.equ I2SR = TWSR ; For compatibility
.equ TWPS0 = 0 ; TWI Prescaler
.equ TWS0 = TWPS0 ; For compatibility
.equ I2GCE = TWPS0 ; For compatibility
.equ TWPS1 = 1 ; TWI Prescaler
.equ TWS1 = TWPS1 ; For compatibility
.equ TWS3 = 3 ; TWI Status
.equ I2S3 = TWS3 ; For compatibility
.equ TWS4 = 4 ; TWI Status
.equ I2S4 = TWS4 ; For compatibility
.equ TWS5 = 5 ; TWI Status
.equ I2S5 = TWS5 ; For compatibility
.equ TWS6 = 6 ; TWI Status
.equ I2S6 = TWS6 ; For compatibility
.equ TWS7 = 7 ; TWI Status
.equ I2S7 = TWS7 ; For compatibility
; TWDR - TWI Data register
.equ I2DR = TWDR ; For compatibility
.equ TWD0 = 0 ; TWI Data Register Bit 0
.equ TWD1 = 1 ; TWI Data Register Bit 1
.equ TWD2 = 2 ; TWI Data Register Bit 2
.equ TWD3 = 3 ; TWI Data Register Bit 3
.equ TWD4 = 4 ; TWI Data Register Bit 4
.equ TWD5 = 5 ; TWI Data Register Bit 5
.equ TWD6 = 6 ; TWI Data Register Bit 6
.equ TWD7 = 7 ; TWI Data Register Bit 7
; TWAR - TWI (Slave) Address register
.equ I2AR = TWAR ; For compatibility
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDTCSR = WDTCR ; For compatibility
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDTOE = WDCE ; For compatibility
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
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