init.s

The latest release, ver 1.16 of the ARM (7TDMI, 720T, 920T) port for uC/OS-II V2.61 (and higher) inc

;**************************************************************************
;                                                                         *
;   PROJECT     : ARM port for uC/OS-II                                   *
;                                                                         *
;   MODULE      : INIT.s                                                  *
;                                                                         *
;   AUTHOR      : Michael Anburaj                                         *
;                 URL  : http://geocities.com/michaelanburaj/             *
;                 EMAIL: [e-mail]                       *
;                                                                         *
;   SPONSORS    : Thanks to Martin Li ([e-mail]) & Don Williams    *
;                 ([e-mail]) for sponsoring hardware.            *
;                                                                         *
;   PROCESSOR   : LPC210x (32 bit ARM7TDMI-S RISC core from Philips)      *
;                                                                         *
;   TOOL-CHAIN  : SDT 2.51 or ADS 1.2                                     *
;                                                                         *
;   DESCRIPTION :                                                         *
;   LPC210x processor Start up assembly code file.                        *
;                                                                         *
;*************************************************************************/


        GET armdefs.a


SRAM_SADDR    EQU 0x40000000           ; SRAM starting address
    [ LPC2104
SRAM_SIZE     EQU 16*1024               ; 16K internal SRAM
    ]
    [ LPC2105
SRAM_SIZE     EQU 32*1024               ; 32K internal SRAM
    ]
    [ LPC2106
SRAM_SIZE     EQU 64*1024               ; 64K internal SRAM
    ]
    [ LPC2131
SRAM_SIZE     EQU  8*1024               ; 8K internal SRAM
    ]
    [ LPC2132
SRAM_SIZE     EQU 16*1024               ; 16K internal SRAM
    ]
    [ LPC2134
SRAM_SIZE     EQU 16*1024               ; 16K internal SRAM
    ]
    [ LPC2136
SRAM_SIZE     EQU 32*1024               ; 32K internal SRAM
    ]
    [ LPC2138
SRAM_SIZE     EQU 32*1024               ; 32K internal SRAM
    ]

ISR_BADDR     EQU 0x40000000           ; ISR vector table start address

SRAM_EADDR    EQU SRAM_SADDR+SRAM_SIZE-1 ; SRAM end address

_SVC_STKSIZE  EQU 256
    [ UNDEF_EXCEP_APP
_UND_STKSIZE  EQU 256
    |
_UND_STKSIZE  EQU 0
    ]
_ABT_STKSIZE  EQU 256
_IRQ_STKSIZE  EQU 256
_FIQ_STKSIZE  EQU 256

STK_SIZE      EQU _SVC_STKSIZE+_UND_STKSIZE+_ABT_STKSIZE+_IRQ_STKSIZE+_FIQ_STKSIZE

STK_SADDR     EQU SRAM_EADDR+1-STK_SIZE


        MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
        sub sp,sp,#4
        stmfd sp!,{r0}
        ldr r0,=$HandleLabel
        ldr r0,[r0]
        str r0,[sp,#4]
        ldmfd sp!,{r0,pc}
        MEND


;*****************************************************************************
; Hardware vectors
;*****************************************************************************

        AREA  |Init|, CODE, READONLY

        ENTRY

        b ResetHandler
        b HandlerUndef                 ; handlerUndef
        b HandlerSWI                   ; SWI interrupt handler
        b HandlerPabort                ; handlerPAbort
        b HandlerDabort                ; handlerDAbort
        b .                            ; handlerReserved
        b HandlerIRQ                   ; handlerIRQ
        b HandlerFIQ                   ; handlerFIQ
   
HandlerFIQ     HANDLER HandleFIQ
HandlerIRQ     HANDLER HandleIRQ
HandlerUndef   HANDLER HandleUndef
HandlerSWI     HANDLER HandleSWI
HandlerDabort  HANDLER HandleDabort
HandlerPabort  HANDLER HandlePabort


;*****************************************************************************
; ResetHandler - Code executed after Reset
;*****************************************************************************
ResetHandler
        ; Initialize stacks
        bl InitStacks

        ; Copy the initialized data block (.data) from ROM to RAM.
        ; Zero out the uninitialized data block (.bss)
        IMPORT  |Load$$DATA$$Base|, WEAK        ; Load address of DATA region
        IMPORT  |Image$$DATA$$Base|, WEAK       ; Execute address of DATA region
        IMPORT  |Image$$DATA$$Length|, WEAK     ; Length of DATA region
        IMPORT  |Image$$DATA$$ZI$$Base|, WEAK   ; Base address of DATA-ZI region
        IMPORT  |Image$$DATA$$ZI$$Length|, WEAK ; Length of DATA-ZI region

        ldr r0,=|Load$$DATA$$Base|     ; Get pointer to ROM data
        ldr r1,=|Image$$DATA$$Base|    ; and RAM copy
        ldr r3,=|Image$$DATA$$Length|
        add r3,r3,r1                   ; End address of DATA region
                        
        cmp r0,r1                      ; Check that they are different
        beq %F1
0
        cmp r1,r3                      ; Copy init data
        ldrcc r2,[r0],#4
        strcc r2,[r1],#4
        bcc %B0
1
        ldr r3,=|Image$$DATA$$ZI$$Base|
        ldr r1,=|Image$$DATA$$ZI$$Length| ; Top of zero init segment
        mov r2,#0
2
        cmp r3,r1                      ; Zero init
        strcc r2,[r3],#4
        bcc %B2

program
        ; Call the actual C program.
        ; Should never return.
        IMPORT C_vMain
        b C_vMain                      ; C Entry (Arm/Thumb)


;*****************************************************************************
; InitStacks - Initializes stack pointer for all the processor modes
;*****************************************************************************
InitStacks
        mrs r0,cpsr
        bic r0,r0,#MODEMASK
    [ UNDEF_EXCEP_APP
        orr r1,r0,#UNDEFMODE|NOINT
        msr cpsr_cxsf,r1               ; UndefMode
        ldr sp,=UndefStack
    ]
        orr r1,r0,#ABORTMODE|NOINT
        msr cpsr_cxsf,r1               ; AbortMode
        ldr sp,=AbortStack

        orr r1,r0,#IRQMODE|NOINT
        msr cpsr_cxsf,r1               ; IRQMode
        ldr sp,=IRQStack
        
        orr r1,r0,#FIQMODE|NOINT
        msr cpsr_cxsf,r1               ; FIQMode
        ldr sp,=FIQStack

        bic r0,r0,#MODEMASK|NOINT
        orr r1,r0,#SVCMODE
        msr cpsr_cxsf,r1               ; SVCMode
        ldr sp,=SVCStack

        ; USER mode is not initialized.

        mov pc,lr


;*****************************************************************************
; Stack memory buffers for all the processor modes
;*****************************************************************************

        AREA  SYS_STK, DATA, READWRITE, NOINIT

        ^       STK_SADDR

UserStack       #       _SVC_STKSIZE
SVCStack        #       _UND_STKSIZE
UndefStack      #       _ABT_STKSIZE
AbortStack      #       _IRQ_STKSIZE
IRQStack        #       _FIQ_STKSIZE
FIQStack        #       0 


;*****************************************************************************
; Software vector table for all the exceptions
;*****************************************************************************

        AREA  ISR_HOOK, DATA, READWRITE, NOINIT

        ^  ISR_BADDR
HandleReset     # 4
HandleUndef     # 4
HandleSWI       # 4
HandlePabort    # 4
HandleDabort    # 4
HandleReserved  # 4
HandleIRQ       # 4
HandleFIQ       # 4


;
;*****************************************************************************
;
        END