lpc210x.h

The latest release, ver 1.16 of the ARM (7TDMI, 720T, 920T) port for uC/OS-II V2.61 (and higher) inc

#define BIT_IR_CR2      (1 << 6)
#define BIT_IR_CR3      (1 << 7)

// Timer Control Register Bit Definitions
#define BIT_TCR_ENABLE  (1 << 0)
#define BIT_TCR_RESET   (1 << 1)

// Timer Match Control Register Bit Definitions
#define BIT_MCR_MR0_I   (1 << 0)            // Enable Interrupt when MR0 matches TC
#define BIT_MCR_MR0_R   (1 << 1)            // Enable Reset of TC upon MR0 match
#define BIT_MCR_MR0_S   (1 << 2)            // Enable Stop of TC upon MR0 match
#define BIT_MCR_MR1_I   (1 << 3)            // Enable Interrupt when MR1 matches TC
#define BIT_MCR_MR1_R   (1 << 4)            // Enable Reset of TC upon MR1 match
#define BIT_MCR_MR1_S   (1 << 5)            // Enable Stop of TC upon MR1 match
#define BIT_MCR_MR2_I   (1 << 6)            // Enable Interrupt when MR2 matches TC
#define BIT_MCR_MR2_R   (1 << 7)            // Enable Reset of TC upon MR2 match
#define BIT_MCR_MR2_S   (1 << 8)            // Enable Stop of TC upon MR2 match
#define BIT_MCR_MR3_I   (1 << 9)            // Enable Interrupt when MR3 matches TC
#define BIT_MCR_MR3_R   (1 << 10)           // Enable Reset of TC upon MR3 match
#define BIT_MCR_MR3_S   (1 << 11)           // Enable Stop of TC upon MR3 match


// PWM
#define rPWMIR     (*(volatile unsigned *)(SFR_BADDR + 0x14000))         //Interrupt Register
#define rPWMTCR    (*(volatile unsigned *)(SFR_BADDR + 0x14004))         //Timer Control
#define rPWMTC     (*(volatile unsigned *)(SFR_BADDR + 0x14008))         //Timer Counter
#define rPWMPR     (*(volatile unsigned *)(SFR_BADDR + 0x1400c))         //Prescale Register
#define rPWMPC     (*(volatile unsigned *)(SFR_BADDR + 0x14010))         //Prescale Counter
#define rPWMMCR    (*(volatile unsigned *)(SFR_BADDR + 0x14014))         //Match Control
#define rPWMMR0    (*(volatile unsigned *)(SFR_BADDR + 0x14018))         //Match Register 0
#define rPWMMR1    (*(volatile unsigned *)(SFR_BADDR + 0x1401c))         //Match Register 1
#define rPWMMR2    (*(volatile unsigned *)(SFR_BADDR + 0x14020))         //Match Register 2
#define rPWMMR3    (*(volatile unsigned *)(SFR_BADDR + 0x14024))         //Match Register 3
#define rPWMMR4    (*(volatile unsigned *)(SFR_BADDR + 0x14040))         //Match Register 4
#define rPWMMR5    (*(volatile unsigned *)(SFR_BADDR + 0x14044))         //Match Register 5
#define rPWMMR6    (*(volatile unsigned *)(SFR_BADDR + 0x14048))         //Match Register 6
#define rPWMPCR    (*(volatile unsigned *)(SFR_BADDR + 0x1404c))         //PWM Control
#define rPWMLER    (*(volatile unsigned *)(SFR_BADDR + 0x14050))         //Latch Enable


// RTC
#define rILR       (*(volatile unsigned char *)(SFR_BADDR + 0x24000))    //Interrupt Location Register
#define rCTC       (*(volatile unsigned short *)(SFR_BADDR + 0x24004))   //Clock Tick Counter
#define rCCR       (*(volatile unsigned char *)(SFR_BADDR + 0x24008))    //Clock Control Register
#define rCIIR      (*(volatile unsigned char *)(SFR_BADDR + 0x2400c))    //Counter Increment Interrupt Register
#define rAMR       (*(volatile unsigned char *)(SFR_BADDR + 0x24010))    //Alarm Mask Register
#define rCT1ME0    (*(volatile unsigned *)(SFR_BADDR + 0x24014))         //Consolidated Time Register 0
#define rCT1ME1    (*(volatile unsigned *)(SFR_BADDR + 0x24018))         //Consolidated Time Register 1
#define rCT1ME2    (*(volatile unsigned *)(SFR_BADDR + 0x2401c))         //Consolidated Time Register 2
#define rSEC       (*(volatile unsigned char *)(SFR_BADDR + 0x24020))    //Seconds Register
#define rMIN       (*(volatile unsigned char *)(SFR_BADDR + 0x24024))    //Minutes Register
#define rHOUR      (*(volatile unsigned char *)(SFR_BADDR + 0x24028))    //Hours Register
#define rDOM       (*(volatile unsigned char *)(SFR_BADDR + 0x2402c))    //Day of Month Register
#define rDOW       (*(volatile unsigned char *)(SFR_BADDR + 0x24030))    //Day of Week Register
#define rDOY       (*(volatile unsigned short *)(SFR_BADDR + 0x24034))   //Day of Year Register
#define rMONTH     (*(volatile unsigned char *)(SFR_BADDR + 0x24038))    //Months Register
#define rYEAR      (*(volatile unsigned char *)(SFR_BADDR + 0x2403c))    //Years Register
#define rALSEC     (*(volatile unsigned char *)(SFR_BADDR + 0x24060))    //Alarm value for Seconds
#define rALMIN     (*(volatile unsigned char *)(SFR_BADDR + 0x24064))    //Alarm value for Minutes
#define rALHOUR    (*(volatile unsigned char *)(SFR_BADDR + 0x24068))    //Alarm value for Hours
#define rALDOM     (*(volatile unsigned char *)(SFR_BADDR + 0x2406c))    //Alarm value for Day of Month
#define rALDOW     (*(volatile unsigned char *)(SFR_BADDR + 0x24070))    //Alarm value for Day of Week
#define rALDOY     (*(volatile unsigned short *)(SFR_BADDR + 0x24074))   //Alarm value for Day of Year
#define rALMON     (*(volatile unsigned char *)(SFR_BADDR + 0x24078))    //Alarm value for Months
#define rALYEAR    (*(volatile unsigned short *)(SFR_BADDR + 0x2407c))   //Alarm value for Year
#define rPREINT    (*(volatile unsigned short *)(SFR_BADDR + 0x24080))   //Prescale value, integer portion
#define rPREFRAC   (*(volatile unsigned short *)(SFR_BADDR + 0x24084))   //Prescale value, fractional portion


// Watchdog
#define rWDMOD     (*(volatile unsigned char *)(SFR_BADDR + 0x00000))    //Mode register
#define rWDTC      (*(volatile unsigned *)(SFR_BADDR + 0x00004))         //timer constant register
#define rWDFEED    (*(volatile unsigned char *)(SFR_BADDR + 0x00008))    //feed sequence register
#define rWDTV      (*(volatile unsigned *)(SFR_BADDR + 0x0000c))         //timer value register


// ISR
#define pISR_RESET     (*(unsigned *)(ISR_BADDR+0x0))
#define pISR_UNDEF     (*(unsigned *)(ISR_BADDR+0x4))
#define pISR_SWI       (*(unsigned *)(ISR_BADDR+0x8))
#define pISR_PABORT    (*(unsigned *)(ISR_BADDR+0xc))
#define pISR_DABORT    (*(unsigned *)(ISR_BADDR+0x10))
#define pISR_RESERVED  (*(unsigned *)(ISR_BADDR+0x14))
#define pISR_IRQ       (*(unsigned *)(ISR_BADDR+0x18))
#define pISR_FIQ       (*(unsigned *)(ISR_BADDR+0x1c))

#define aISR_WDT       (ISR_BADDR+0x20)
#define pISR_WDT       (*(unsigned *)aISR_WDT)
#define pISR_RES1      (*(unsigned *)(ISR_BADDR+0x24))
#define pISR_DBGCOMMRX (*(unsigned *)(ISR_BADDR+0x28))
#define pISR_DBGCOMMTX (*(unsigned *)(ISR_BADDR+0x2c))
#define pISR_TIMER0    (*(unsigned *)(ISR_BADDR+0x30))
#define pISR_TIMER1    (*(unsigned *)(ISR_BADDR+0x34))
#define pISR_UART0     (*(unsigned *)(ISR_BADDR+0x38))
#define pISR_UART1     (*(unsigned *)(ISR_BADDR+0x3c))
#define pISR_PWM       (*(unsigned *)(ISR_BADDR+0x40))
#define pISR_I2C       (*(unsigned *)(ISR_BADDR+0x44))
#define pISR_SPI       (*(unsigned *)(ISR_BADDR+0x48))
#define pISR_RES2      (*(unsigned *)(ISR_BADDR+0x4c))
#define pISR_PLL       (*(unsigned *)(ISR_BADDR+0x50))
#define pISR_RTC       (*(unsigned *)(ISR_BADDR+0x54))
#define pISR_EINT0     (*(unsigned *)(ISR_BADDR+0x58))
#define pISR_EINT1     (*(unsigned *)(ISR_BADDR+0x5c))
#define pISR_EINT2     (*(unsigned *)(ISR_BADDR+0x60))


// PENDING BIT
#define BIT_WDT        (0x1<<0)
#define BIT_RES1       (0x1<<1)
#define BIT_DBGCOMMRX  (0x1<<2)
#define BIT_DBGCOMMTX  (0x1<<3)
#define BIT_TIMER0     (0x1<<4)
#define BIT_TIMER1     (0x1<<5)
#define BIT_UART0      (0x1<<6)
#define BIT_UART1      (0x1<<7)
#define BIT_PWM        (0x1<<8)
#define BIT_I2C        (0x1<<9)
#define BIT_SPI        (0x1<<10)
#define BIT_RES2       (0x1<<11)
#define BIT_PLL        (0x1<<12)
#define BIT_RTC        (0x1<<13)
#define BIT_EINT0      (0x1<<14)
#define BIT_EINT1      (0x1<<15)
#define BIT_EINT2      (0x1<<16)

#define MIN_INT_NUM    0
#define MAX_INT_NUM    16

#define INT_SELECT_IRQ(bit)   \
{                             \
    rVICIntSelect &= ~bit;    \
}

#define INT_SELECT_FIQ(bit)   \
{                             \
    rVICIntSelect |= bit;     \
}

/* sel = IRQ or FIQ */
#define INT_ENABLE(sel, bit)  \
{                             \
    INT_SELECT_ ##sel(bit);   \
    rVICIntEnable = bit;      \
}

#define INT_DISABLE(bit)      \
{                             \
    rVICIntEnClear = bit;     \
}

// PLL defines & computations
// Compute the value of PLL_DIV and test range validity
// FOSC & PLL_MUL should be defined in project configuration file (frmwrk.h)
#ifndef CCLK
#define CCLK          (FOSC * PLL_MUL)                            //CPU Clock Freq.
#endif

#define FCCO_MAX      (320000000)                                 //Max CC Osc Freq.
#define PLL_DIV       (FCCO_MAX / (2 * CCLK))                     //PLL Divider
#define FCCO          (FOSC * PLL_MUL * 2 * PLL_DIV)              //CC Osc. Freq.

// rPLLCFG Register values
#define VAL_PLLCFG_MSEL  ((PLL_MUL - 1) << 0)                     //PLL Multiplier
#define VAL_PLLCFG_PSEL  ((PLL_DIV - 1) << 5)                     //PLL Divider

// Clock value range tests
#if ((FOSC < 10000000) || (FOSC > 25000000))
#error FOSC is out of range (10MHz-25MHz)
#endif

#if ((CCLK < 10000000) || (CCLK > 60000000))
#error CCLK is out of range (10MHz-60MHz)
#endif

#if ((PLL_MUL != 1) && (PLL_MUL != 2) && (PLL_MUL != 3) && (PLL_MUL != 4) && (PLL_MUL != 5) && (PLL_MUL != 6))
#error PLL_MUL illegal value (whole number between 1 & 6), change the value of CCLK accordingly
#endif

#if ((FCCO < 156000000) || (FCCO > 320000000))
#error FCCO is out of range (156MHz-320MHz), Check the PLL calculation
#endif


// MAM defines
#define VAL_MAMCR_OFF     0
#define VAL_MAMCR_PART    1
#define VAL_MAMCR_FULL    2

#define VAL_MAMTIM_CYCLES (((CCLK) + 19999999) / 20000000)


// MEMMAP defines
#define VAL_MEMMAP_BBLK   0                 //Interrupt Vectors in Boot Block
#define VAL_MEMMAP_FLASH  1                 //Interrupt Vectors in Flash
#define VAL_MEMMAP_SRAM   2                 //Interrupt Vectors in SRAM


// VPBDIV defines
#define VAL_VPBDIV  (PBSD & 0x03)           //VPBDIV value

#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))
#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)
#endif


// CAUTION - 'baud' SHOULD ALWAYS BE A CONSTANT or
// a lot of code will be generated.
#define UART_BAUD(baud) (unsigned short)((PCLK / ((baud) * 16.0)) + 0.5)


/* ********************************************************************* */
/* Interface function definition */


/* ********************************************************************* */

#ifdef __cplusplus
}
#endif

#endif /*__LPC210X_H__*/