pc.h

鼎鼎大名的WRS提供的VxWorks下pcPentium BSP开发包

/* pc.h - PC 386 header */

/*
modification history
--------------------
02d,08feb99,jkf  removed PCI_CFG_* definitions, now set in configAll.h
02c,28may98,hdn  added support for APIC.
02b,13may98,hdn  moved PAGE_SIZE_XXX macro to mmuI86Lib.h and include it.
		 added UNUSED_ISA_IO_ADDRESS for IO address 0x84.
02a,16apr98,hdn  added PAGE_SIZE_XXX macro for PentiumPro.
01z,17mar98,sbs  added definitions for dynamic mmu entries.
01y,12mar98,sbs  changed SCSI-2 definitions to device specific definitions. 
                 Added PCI configuration definitions and FEI specific 
                 definitions. 
01x,10jul97,dds  added SCSI-2 support.
01w,16jan97,hdn  added PCMCIA_SOCKS, PCMCIA_MEMBASE.
01v,03dec96,hdn  renamed PCI_FEIxxx to FEIxxx.
01u,20nov96,hdn  added support for PRO100B.
01t,01nov96,hdn  added support for PCMCIA.
01s,21oct96,hdn  added new configuration macros for LPT: LPT_xxx.
01r,12oct96,hdn  added support for ATA-2.  changed ATA[01]_CONFIG.
01q,03sep96,hdn  added the compression support.
01p,09aug96,hdn  renamed INT_VEC_IRQ0 to INT_NUM_IRQ0.
01o,19jul96,hdn  added support for ATA driver.
01n,25jun96,hdn  added support for TIMESTAMP timer.
01m,28may96,hdn  renamed PIT_INT_xxx to PIT0_INT_xxx.
01l,14jun95,myz  removed #include tyLib.h
01k,21oct94,hdn  deleted ENABLE_A20 macro.
01j,15oct94,hdn  added macros for LPT parallel driver.
01i,25apr94,hdn  moved a macro PC_KBD_TYPE to config.h.
01h,08nov93,vin  added support for pc console drivers.
01g,12oct93,hdn  added interrupt level macros.
01f,16aug93,hdn  added RTC related macros.
01e,03aug93,hdn  changed vectors for serial and timer.
01d,17jun93,hdn  updated to 5.1.
01c,07apr93,hdn  renamed compaq to pc.
01b,26mar93,hdn  deleted a macro CPU because it supports 386 and 486.
01a,15may92,hdn  written based on frc386 version.
*/

/*
This file contains IO address and related constants for the
PC 386.
*/

#ifndef	INCpch
#define	INCpch

#include "drv/intrCtl/i8259.h"
#include "drv/timer/i8253.h"
#include "drv/timer/mc146818.h"
#include "drv/timer/timerDev.h"
#include "drv/timer/timestampDev.h"
#include "drv/hdisk/ideDrv.h"
#include "drv/fdisk/nec765Fd.h"
#include "drv/serial/pcConsole.h"
#include "drv/parallel/lptDrv.h"
#include "drv/pcmcia/pcmciaLib.h"
#include "drv/hdisk/ataDrv.h"
#include "drv/pci/pciConfigLib.h"
#include "arch/i86/mmuI86Lib.h"

#undef	CAST
#define	CAST

#define TARGET_PC386

#define BUS		VME_BUS		/* XXX */

#define	BOOTCODE_IN_RAM			/* for ../all/bootInit.c */

/* constant values in romInit.s */

#define ROM_IDTR	0xaf		/* offset to romIdtr  */
#define ROM_GDTR	0xb5		/* offset to romGdtr  */
#define ROM_GDT		0xc0		/* offset to romGdt   */
#define ROM_INIT2	0xf0		/* offset to romInit2 */
#define ROM_STACK	0x7000		/* initial stack pointer */
#define ROM_WARM_HIGH	0x10		/* warm start entry p */
#define ROM_WARM_LOW	0x20		/* warm start entry p */

/* programmable interrupt controller (PIC) */

#define	PIC1_BASE_ADR		0x20
#define	PIC2_BASE_ADR		0xa0
#define	PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */

/* serial ports (COM1,COM2) */

#define	COM1_BASE_ADR		0x3f8
#define	COM2_BASE_ADR		0x2f8
#define	COM1_INT_LVL		0x04
#define	COM2_INT_LVL		0x03
#define	UART_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */
#define	N_UART_CHANNELS		2

/* timer (PIT) */

#define	PIT_BASE_ADR		0x40
#define	PIT0_INT_LVL		0x00
#define	PIT_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */
#define	PIT_CLOCK		1193180

/* real time clock (RTC) */

#define	RTC_INDEX		0x70
#define	RTC_DATA		0x71
#define	RTC_INT_LVL		0x08

/* floppy disk (FD) */

#define FD_INT_LVL              0x06
#define FD_DMA_BUF_ADDR		0x2000	/* floppy disk DMA buffer address */
#define FD_DMA_BUF_SIZE		0x3000	/* floppy disk DMA buffer size */

/* hard disk (IDE) */

#define IDE_CONFIG		0x0	/* 1: uses ideTypes table */
#define IDE_INT_LVL             0x0e

/* hard disk (ATA) */

#define ATA0_IO_START0		0x1f0	/* io for ATA0 */
#define ATA0_IO_STOP0		0x1f7
#define ATA0_IO_START1		0x3f6
#define ATA0_IO_STOP1		0x3f7
#define ATA0_INT_LVL            0x0e
#define ATA0_CONFIG		(ATA_GEO_CURRENT | ATA_PIO_AUTO | \
				 ATA_BITS_16 | ATA_PIO_MULTI)
#define ATA1_IO_START0		0x170	/* io for ATA1 */
#define ATA1_IO_STOP0		0x177
#define ATA1_IO_START1		0x376
#define ATA1_IO_STOP1		0x377
#define ATA1_INT_LVL		0x09	/* 9 for PCIC. 5 for TCIC */
#define ATA1_CONFIG		(ATA_GEO_CURRENT | ATA_PIO_AUTO | \
				 ATA_BITS_16 | ATA_PIO_MULTI)
#define ATA_SEM_TIMEOUT		5       /* timeout for ATA sync sem */
#define ATA_WDG_TIMEOUT		5       /* timeout for ATA watch dog */

/* pcmcia (PCMCIA) */

#define PCMCIA_SOCKS		0x0	/* number of sockets. 0=auto detect */
#define PCMCIA_MEMBASE		0x0	/* mapping base address */
#define PCIC_BASE_ADR           0x3e0	/* Intel 82365SL */
#define PCIC_INT_LVL            0x0a
#define TCIC_BASE_ADR           0x240	/* Databook DB86082A */
#define TCIC_INT_LVL            0x0a
#define CIS_MEM_START           0xd0000	/* mapping addr for CIS tuple */
#define CIS_MEM_STOP            0xd3fff
#define CIS_REG_START           0xd4000	/* mapping addr for config reg */
#define CIS_REG_STOP            0xd4fff
#define SRAM0_MEM_START		0xd8000	/* mem for SRAM0 */
#define SRAM0_MEM_STOP		0xd8fff
#define SRAM0_MEM_LENGTH	0x100000
#define SRAM1_MEM_START		0xd9000	/* mem for SRAM1 */
#define SRAM1_MEM_STOP		0xd9fff
#define SRAM1_MEM_LENGTH	0x100000
#define SRAM2_MEM_START		0xda000	/* mem for SRAM2 */
#define SRAM2_MEM_STOP		0xdafff
#define SRAM2_MEM_LENGTH	0x100000
#define SRAM3_MEM_START		0xdb000	/* mem for SRAM3 */
#define SRAM3_MEM_STOP		0xdbfff
#define SRAM3_MEM_LENGTH	0x100000
#define ELT0_IO_START		0x260	/* io for ELT0 */
#define ELT0_IO_STOP		0x26f
#define ELT0_INT_LVL		0x05
#define ELT0_NRF		0x00
#define ELT0_CONFIG		0	/* 0=EEPROM 1=AUI  2=BNC  3=RJ45 */
#define ELT1_IO_START		0x280	/* io for ELT1 */
#define ELT1_IO_STOP		0x28f
#define ELT1_INT_LVL		0x09
#define ELT1_NRF		0x00
#define ELT1_CONFIG		0	/* 0=EEPROM 1=AUI  2=BNC  3=RJ45 */

/* parallel port (LPT) */

#define LPT0_BASE_ADRS		0x3bc
#define LPT1_BASE_ADRS		0x378
#define LPT2_BASE_ADRS		0x278
#define LPT_INT_LVL             0x07
#define LPT_CHANNELS		1

/* ISA IO address for sysDelay () */

#define UNUSED_ISA_IO_ADDRESS	0x84

/* FEI PCI bus resources */

#define FEI0_MEMBASE0		0xfd000000	/* memory base for CSR */
#define FEI0_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI0_MEMBASE1		0xfd100000	/* memory base for Flash */
#define FEI0_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI0_IOBASE0		0xf400		/* IO base for CSR, 32Bytes */
#define FEI0_INT_LVL		0x0b		/* IRQ 11 */
#define FEI0_INIT_STATE_MASK	(VM_STATE_MASK_FOR_ALL)
#define FEI0_INIT_STATE		(VM_STATE_FOR_PCI)
#define FEI1_MEMBASE0		0xfd200000	/* memory base for CSR */
#define FEI1_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI1_MEMBASE1		0xfd300000	/* memory base for Flash */
#define FEI1_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI1_IOBASE0		0xf420		/* IO base for CSR, 32Bytes */
#define FEI1_INT_LVL		0x05		/* IRQ 5 */
#define FEI1_INIT_STATE_MASK    (VM_STATE_MASK_FOR_ALL)
#define FEI1_INIT_STATE         (VM_STATE_FOR_PCI)
#define FEI2_MEMBASE0		0xfd400000	/* memory base for CSR */
#define FEI2_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI2_MEMBASE1		0xfd500000	/* memory base for Flash */
#define FEI2_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI2_IOBASE0		0xf440		/* IO base for CSR, 32Bytes */
#define FEI2_INT_LVL		0x0c		/* IRQ 12 */
#define FEI2_INIT_STATE_MASK    (VM_STATE_MASK_FOR_ALL)
#define FEI2_INIT_STATE         (VM_STATE_FOR_PCI)
#define FEI3_MEMBASE0		0xfd600000	/* memory base for CSR */
#define FEI3_MEMSIZE0		0x00001000	/* memory size for CSR, 4KB */
#define FEI3_MEMBASE1		0xfd700000	/* memory base for Flash */
#define FEI3_MEMSIZE1		0x00100000	/* memory size for Flash, 1MB */
#define FEI3_IOBASE0		0xf460		/* IO base for CSR, 32Bytes */
#define FEI3_INT_LVL		0x09		/* IRQ 9 */
#define FEI3_INIT_STATE_MASK    (VM_STATE_MASK_FOR_ALL)
#define FEI3_INIT_STATE         (VM_STATE_FOR_PCI)

/* AIC7880 PCI bus resources */

#define AIC7880_MEMBASE  	0xf5200000	
#define AIC7880_MEMSIZE		0x00001000	/* memory size for CSR, 4KB */
#define AIC7880_IOBASE		0xf800	
#define AIC7880_INT_LVL		0x0a
#define AIC7880_INIT_STATE_MASK (VM_STATE_MASK_FOR_ALL)
#define AIC7880_INIT_STATE      (VM_STATE_FOR_IO)

/* key board (KBD) */

#define PC_XT_83_KBD		0	/* 83 KEY PC/PCXT/PORTABLE 	*/
#define PC_PS2_101_KBD		1	/* 101 KEY PS/2 		*/
#define KBD_INT_LVL		0x01

#define	COMMAND_8042		0x64
#define	DATA_8042		0x60
#define	STATUS_8042		COMMAND_8042
#define COMMAND_8048		0x61	/* out Port PC 61H in the 8255 PPI */
#define	DATA_8048		0x60	/* input port */
#define	STATUS_8048		COMMAND_8048

#define JAPANES_KBD             0
#define ENGLISH_KBD             1

/* beep generator */

#define DIAG_CTRL	0x61
#define BEEP_PITCH_L	1280 /* 932 Hz */
#define BEEP_PITCH_S	1208 /* 987 Hz */
#define BEEP_TIME_L	(sysClkRateGet () / 3) /* 0.66 sec */
#define BEEP_TIME_S	(sysClkRateGet () / 8) /* 0.15 sec */

/* Monitor definitions */

#define MONOCHROME              0
#define VGA                     1
#define MONO			0
#define COLOR			1
#define	VGA_MEM_BASE		(UCHAR *) 0xb8000
#define	VGA_SEL_REG		(UCHAR *) 0x3d4
#define VGA_VAL_REG             (UCHAR *) 0x3d5
#define MONO_MEM_BASE           (UCHAR *) 0xb0000
#define MONO_SEL_REG            (UCHAR *) 0x3b4
#define MONO_VAL_REG            (UCHAR *) 0x3b5
#define	CHR			2

/* change this to JAPANES_KBD if Japanese enhanced mode wanted */

#define KEYBRD_MODE             ENGLISH_KBD 

/* undefine this if ansi escape sequence not wanted */

#define INCLUDE_ANSI_ESC_SEQUENCE 

#define GRAPH_ADAPTER   VGA

#if (GRAPH_ADAPTER == MONOCHROME)

#define DEFAULT_FG  	ATRB_FG_WHITE
#define DEFAULT_BG 	ATRB_BG_BLACK
#define DEFAULT_ATR     DEFAULT_FG | DEFAULT_BG
#define CTRL_SEL_REG	MONO_SEL_REG		/* controller select reg */
#define CTRL_VAL_REG	MONO_VAL_REG		/* controller value reg */
#define CTRL_MEM_BASE	MONO_MEM_BASE		/* controller memory base */
#define COLOR_MODE	MONO			/* color mode */

#else /* GRAPH_ADAPTER = VGA */

#define DEFAULT_FG	ATRB_FG_BRIGHTWHITE
#define DEFAULT_BG	ATRB_BG_BLUE
#define DEFAULT_ATR	DEFAULT_FG | DEFAULT_BG
#define CTRL_SEL_REG	VGA_SEL_REG		/* controller select reg */
#define CTRL_VAL_REG	VGA_VAL_REG		/* controller value reg */
#define CTRL_MEM_BASE	VGA_MEM_BASE		/* controller memory base */
#define COLOR_MODE	COLOR			/* color mode */

#endif /* (ADAPTER == MONOCHROME) */

/*
 * sysPhysMemDesc[] dummy entries:
 * these create space for updating sysPhysMemDesc table at a later stage
 * mainly to provide plug and play
 */

#define DUMMY_PHYS_ADDR         -1
#define DUMMY_VIRT_ADDR         -1
#define DUMMY_LENGTH            -1
#define DUMMY_INIT_STATE_MASK   -1
#define DUMMY_INIT_STATE        -1

#define DUMMY_MMU_ENTRY		{ (void *) DUMMY_PHYS_ADDR, \
                                  (void *) DUMMY_VIRT_ADDR, \
                                  DUMMY_LENGTH, \
                                  DUMMY_INIT_STATE_MASK, \
                                  DUMMY_INIT_STATE \
                                }

/* PCI device configuration type definitions */
#define PCI_CFG_TYPE		PCI_CFG_NONE	/* specify PCI configuartion type */

/* APIC (IO APIC + Local APIC) */

#define IOAPIC_BASE		0xfec00000      /* IO APIC Base Address */
#define IOAPIC_LENGTH		0x00010000      /* IO APIC registers length */
#define LOAPIC_BASE		0xfee00000      /* Local APIC Base Address */
#define LOAPIC_LENGTH		0x00001000      /* Local APIC registers length */
#define EBDA_START		0x9fc00		/* Extended BIOS Data Area */ 
#define EBDA_END		0x9ffff
#define BIOS_ROM_START		0xf0000		/* BIOS ROM space */
#define BIOS_ROM_END		0xfffff

/* Local APIC Timer, Spurious, Error */

#define TIMER_CLOCK_HZ          60000000	/* 60Mhz */
#define TIMER_INT_LVL           0		/* any number for WindView */
#define SPURIOUS_INT_LVL        24		/* any number for WindView */
#define ERROR_INT_LVL           25		/* any number for WindView */


#endif	/* INCpch */